P9.2. DC Evaluation of the Single-Power-Supply Differential Amplifier
Components
RD1 = RD2 = RD
Rs = RD/2
VD ≈ VDD/2 – VSG
For Chan0_out = 10 V:
100 μA<ID <400 μA
(Choose One)
RG <100 kΩ
Match the gate resistors on each side to obtain VG = VDD/2. On a given side, the resistors must be equal, but can be different on opposite sides.
Procedure
After completing the circuit connections, open DC.vi. Set Chan0_out = 10 V and run the VI. DC.vi scans Chan1_out to balance the circuit (i.e., to set VD1 = VD2 within 20 mV). Try Chan0_out in the range 5 to 10 V. Verify that 100 μA<ID<400 μA (your design) with maximum Chan0_out = 10 V.
Note the value sent out by Chan1_out. This should be only mV if the gate resistors were selected properly.
Verify that VSD is roughly 2VSG. Default and save the Front Panel with Chan0_out = 10 V. The VI serves as a subVI in the next part to bias and balance the circuit.