The transistor output characteristics from Unit 3 and the variable increments along with their linear relationships are illustrated in Fig. 4.7. This would be applicable, for example, to the amplifier of Fig. 2.4. (As in that circuit, no body effect is included.) The circuit is biased with drain – source voltage VDS and drain current ID. A positive signal Vg is applied to the gate terminal. In response, there appears drain signal voltage –Vd, due to the rise in drain current. Signal voltages are with respect to the source or ground.
The two output characteristic curves correspond to bias VGS only and with gate voltage VGS + Vg. In both cases, the solution to the drain current and voltage is the intersection between the transistor characteristic curve and the load line, which is a plot of the output circuit loop equation. This is (with reference, for example, to Fig. 2.4)
Equation 4.19
The solution is always constrained to this straight-line equation. The solution for vDS with and without signal is based on (4.19) and (3.8), which is
The combined contributions to Id associated with the two g parameters is
Equation 4.20
By the nature of the load-line function, the two terms will always have opposite signs; when Vg is negative, Vd will be positive.
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