7.1. DC (Bias) Circuit
The circuit diagram shown in Fig. 7.1 uses for the transistor a symbol that includes the body connection. This is to emphasize the fact that the output (source) of the source follower is generally (and usually) at different dc and signal potentials from the body. In Project 8 we measure the gain for both the connection shown (which we can make for this special case of one transistor on the chip being used) and with the body connected to VSS, which is signal ground. The latter demonstrates the extent of the influence that the body effect has on the gain when it is not possible to connect the body and source together as shown in Fig. 7.1.
Figure 7.1. Source-follower (common-drain) stage (NMOS transistor) with the input at the gate and the output at the source. In this example, the source is connected to the body. Usually, in a circuit, the body will be attached to the power supply VSS (NMOS).
The design of the stage will often consist of setting the dc output at VO = 0 V (for a dual power supply), as this will be the final (output) stage. Therefore, RS will be selected based on the design drain current from RS = |VSS|/ID. It is then necessary to determine VGS in order to determine the VG = VGS required (which will be set by the dc circuitry of the preceding circuit).
For the usual practical application, body voltage, VB = VSS. With VS = 0 V, VSB = |VSS|. Thus, the threshold voltage, including body effect, will be
Equation 7.1
and the gate bias voltage will be obtainable from
Equation 7.2
If the source and body are connected, as in Fig. 7.1, Vtn is replaced with Vtno.