5.3. Linearity of the Gain of the Common-Source Amplifier

The connection between I_d and V_gs is linear provided that V_gs is small enough, as considered in the following units. Use of the linear relations also assumes that the output signal remains in the active region (i.e., neither in the linear region nor near cutoff). This is discussed below. NMOS subscripts are used. The results are the same for the PMOS, with a “p” subscript substituted for “n” and the subscript order reversed for all bias-voltage variables.

5.3.1. Nonlinearity Referred to the Input

The general equation again is (3.8)

Then using I_d = i_D – I_D and v_GS = V_GS + V_gs, the equation for the incremental drain current becomes

Equation 5.8

which leads to a nonlinear (variable) transconductance, , given by

Equation 5.9

Therefore, the condition for linearity is that V_gs << 2V_eff, with V_effn = V_GS = V_tno and using .

With this condition not satisfied, an output signal is distorted. However, for the purpose of measuring the amplifier gain, our signal voltmeter will take the average of the positive and negative peaks, which is

Equation 5.10

In the parabolic relationship, the squared terms cancel entirely. In general, though, the output signal contains harmonic content (distortion) when V_gs is too large compared to V_effn.

5.3.2. Nonlinearity Referred to the Output

The discussion above of limits imposed on V_gs assumes that the transistor remains in the active mode. To clarify this point, reference is made to the output characteristics of Fig. 5.5. The graph has plots of the output characteristic for three values of v_GS in addition to the load line. The characteristic plot in the midrange is for no signal. Operating point variables are V_DS ≈ 2.5 V and I_D ≈ 40 μA. With a large, positive V_gs, the characteristic moves up to the high-level plot (i_Dhi) and the opposite occurs for a large but negative V_gs (i_Dlo). The high-level plot is shown for when the transistor is about to move out of the active region and into the linear region. Attempts to force v_DS to lower values will create considerable distortion in the output signal voltage. The lower curve suggests that the positive output signal is on the verge of being cut off (clipped) for an additional increase in the negative-input signal voltage.

According to the discussion above, the negative signal output voltage is limited to

Equation 5.11

Technically, V_effn is from the high-current signal state, but for simplicity, a reasonable estimate can be made from the dc case; that is, V_effn = V_GS – V_tno. The positive signal limit is

Equation 5.12

The actual output-signal limit is dictated by the smaller of the two for a symmetrical periodic signal such as a sine-wave. In the example shown in Fig. 5.5, V_effn ≈ 0.5 V, V_DS ≈ 2.5 V, and V_DD = 5 V. The plus and minus signal-voltage limits are about 2.5 V and 2.0 V, respectively. Depending on the dc bias, the limit could be dictated by one or the other. In the amplifier projects, the gain will typically be measured over a range of dc bias current for a fixed resistor. This means that for the low-current end of the scan, the signal will be limited by the magnitude of I_DR_D and, by design, the plus and minus swings will be made to be about equal at the highest dc current.

Distortion associated with the nonlinear I_d – V_gs relation and that due to signal limits at the output may be taking place simultaneously. This is seen from the gain expression (5.7) (g_ds = 0)

where a_v ≡ V_ds/V_gs and where the approximation is for the case of neglecting the λ_n factor. Thus, for a given V_ds, V_gs is

Equation 5.13

If, for example, V_ds is pushed to the positive output-signal limit, then V_ds ≈ V_RD. According to (5.13), V_gs = V_effp/2, and V_gs exceeds the condition for a linear I_d – V_gs relation as given in (5.9),