14.4. Current-Source Load for the Differential Stage

The load resistor (or bias resistor) of the differential stage will now be replaced with a current-source load. In addition to eliminating the need again for a resistor, it provides for much better dc stability and a significant gain improvement, including the elimination of the factor of ½ associated with the differential stage gain as in (8.15) and (8.17).

As shown in the new circuit in Fig. 14.3, the resistor R_D2 is replaced by transistors M₄ and M₅. Transistor M₅ provides a current-source load for transistor M₂. The diode-connected transistor, M₄, provides the dc reference voltage for M₅. The reference current is I_D1 = I_D4.

The dc output voltage (of the differential stage) is set automatically at V_DD – V_SG4 due to the relation V_SD4 = V_SG4 = V_SG5 = V_SD5. This is an idealization that assumes that the parameters of transistors M₄ and M₅ and M₁ and M₂ are identical and that I_D1 = I_D2.

Recall that in the differential stage with drain resistor, R_D2, the noninverting output signal voltage was induced across R_D2 due to the signal current I_d2. In the new circuit, the output current is the composite of signal currents I_d2 and I_d5. That is, signal current I_d1 is mirrored at the output as I_d5. This is a result of the coupling from M₁ through M₄ to the gate of M₅. The circuit from the gate of M₁ to the drain of M₅ can be regarded as a cascade of two common-source stages (M₁ and M₅) with a shunt resistor between them of magnitude 1/g_m4 (the signal resistance of the diode-connected transistor).

The gain for this circuit can be explained starting from the transconductance for the two currents I_d2 and I_d5. Assume for a moment that the output voltage is held constant at the dc bias value. This is equivalent to a signal short circuit at the output. As in the case of the resistor-bias differential amplifier stage, we have

Equation 14.11

where the effect of the output resistance of M₁₁ is neglected. But also, as in the resistor-load case,

Equation 14.12

But I_d1 = –I_d4 and I_d4 is mirrored as I_d5, which leads to I_d5 = –I_d1. This assumes that M₄ and M₅ are identical. Thus,

Equation 14.13

All signal drain currents are defined as positive into the respective drains.

The output currents summed at the output node, V_o, are (defined positive into the node)

Equation 14.14

The result is valid for v_O = V_O or V_o = 0, as stipulated above. One could imagine attaching a dc supply exactly equal to V_O at the output node. In this case, the output current could readily flow into the node according to (14.14).

For the opposite extreme of having an open circuit at the output, as in Fig. 14.3, the currents I_d2 and I_d5 are dependent on v_D2 = v_D5 = v_O. The deviation of I_o from (14.14) is, as usual, taken care of by including the effect of the output resistance at the output node.

The output resistance is somewhat complicated by feedback effects, which are inherent in this circuit. For assessing the circuit output resistance, a signal circuit is shown in Fig. 14.4 with a test voltage, V_o, applied at the output with both inputs grounded. Resulting currents I_d2 and I_d5 will be considered separately and will be superimposed.

The currents indicated in Fig. 14.4 are for the case of I_d2 of M₂. Looking back into the drain of M₂, the output resistance is affected by emitter degeneration because of the resistance 1/g_m1 between the emitter of M₂ and ground. That is, the resistance looking back into the emitter of M₁ is 1/g_m1. Thus, the resistance looking only back into M₂ is 2r_ds2. However, I_d2 feeds through and around the loop composed of M₂, M₁, M₄, and M₅ such that the total current flowing into the node (exclusive of the separate I_d5 contribution) is 2I_d2. The test voltage is V_o = I_d22r_ds2, due to current I_d2 flowing down into the resistance 2r_ds2 of the drain of M₂. The output resistance associated with the drain of M₂, R_oM2, is based on a total current of 2I_d2 such that it is

Equation 14.15

The drain resistance 2r_ds2 combined with a test current of 2I_d2 results in an effective drain resistance r_ds2 despite the emitter degeneration.

Separately, by superposition, for applied V_o, a current I_d5 of value I_d5 = V_o/r_ds5 flows into the drain of M₅ such that the output resistance associated with M₅ is R_oM5 = r_ds5 = 1/g_ds5. This is based on the fact that the output resistance is that of a common-source stage with grounded source. The two contributions are in parallel such that finally, the output resistance is

Equation 14.16

Combining this with the effective amplifier transconductance obtained above, (14.14), the gain is

Equation 14.17

or

Equation 14.18

An external load, R_L, appears in parallel with R_o. Hence with an external load, the gain is

Equation 14.19

In the discussion leading to (14.14), it was noted that the output current given by (14.14) is for a short-circuit condition at the output, and the effect of finite V_d2 = V_d5 is taken care of through the concept of the output resistance of the circuit. A clarification of this statement is provided by the analytical formulation, which includes a load, R_L, given by

Equation 14.20

where v_D5 = v_D2, as they are the same node. The linear form is

Equation 14.21

and this leads to (14.19), where, again, a_v2 = V_d2/V_g1. A voltage source attached to the output is equivalent to R_L → 0, in which case V_d2 → 0 and v_D2 → V_D2 = V_O, that is, the bias value. The finite output current magnitude into the short circuit is consistent with V_d2/R_L|_{vds, RL→0} = g_m1V_g1.

14.4.1. Common-Mode Gain of the Differential Stage with Current-Source Load

As may be deduced from the common-mode gain equation, (14.2), in Unit 14.2, the common-mode transconductance for the differential stage with current-source biasing is G_m = g_m1/(1 + g_m12r_DS11). The incremental load at the drain of M₁ for the case of the circuit shown in Fig. 14.3, however, is the resistance of the diode-connected transistor M₄ of Fig. 14.3, which is 1/g_m4. Due to symmetry, this is also the effective load at the drain of M₂. The common-mode gain is thus

Equation 14.22

and the common-mode rejection ratio is, from (4.17) (for single-ended output) and (14.22),

Equation 14.23

This is greater than (14.3) by the factor g_m4/(g_ds2 + g_ds5) ≈ [V_eff4(λ_n + λ_p)]^–1.