3.2. Output and Transfer Characteristics of the MOSFET

The equations used in the following to characterize the MOSFET transistor are from the SPICE Level 1 model. SPICE also has more detailed models in Level 2 and Level 3. These can be specified when running SPICE. However, the number of new model parameters, in general, in circuit simulation is practically boundless. Level 1 is chosen here as it is the most intuitive, that is, the most suitable for an introductory discussion of device behavior. Some new models, for example, which focus on frequency response at very high frequencies, can include pages of equations. In addition, Level 1 is suitable and adequate for many examples of circuit simulation.

The basic common-source NMOS circuit configuration is repeated in Fig. 3.2. Here it serves as a basis for discussing the dc SPICE parameters of the MOSFET transistor. In the example, V_DS = V_DD. The output characteristic is a plot of I_D versus V_DS for V_GS = const. A representative example is shown in Fig. 3.3. As mentioned, the low-voltage region is referred to as the linear region, triode region, or presaturation region. Outside this region for higher voltages is the active (saturation) region. This is referred to here as the active region to avoid confusion with the fact that the nomenclature is just the opposite in the case of the BJT; that is, the low-voltage region is called the saturation region. As discussed in Unit 3.1, the linear and active regions are delineated by V_effn ≡ V_DSsat = V_GS – V_tno.

The output-characteristic equation in the linear region corresponds to V_DS ranging from the condition of Fig. 3.1(b) to that of Fig. 3.1(c). As V_DS increases from zero, the channel begins to close off at the drain end (i.e., the channel becomes progressively more wedge shaped). The result is an increase in the resistance of the channel as a function of V_DS, and therefore a sublinear current – voltage relation develops.

When V_GS > V_tno, the electron charge in the channel can be related to the gate voltage by Q_chan = C_ox(V_GS – V_tno) (per unit area of MOSFET looking down at the gate), where C_ox is the parallel-plate capacitance (per unit area) formed by the MOS structure. This provides a simple linear relation between the gate voltage and the charge in the channel.

The conductivity in the channel is σ_chan = μ_nQ_chan/t_chan, where μ_n is the mobility of the electrons in the channel and t_chan is the thickness of the channel into the semiconductor. Thus, in the case of a uniform channel (i.e., for V_DS → 0), the channel conductance is

Equation 3.2

where

Equation 3.3

and where KP_n = μ_nC_ox is the SPICE transconductance parameter (the n subscript is the equation symbolic notation for the NMOS; the parameter in the device model is just KP), W is the physical gate width, and L, again, is the channel length. Parameter KP_n is related to the electron mobility in the channel and the oxide thickness. Therefore, it is very specific to a given MOSFET device.

As V_DS increases, but is less than V_effn [transition from Fig. 3.1(b) to 3.1(c)], the wedge-shaped effect on the channel is reflected functionally in the channel conductance relation as

Equation 3.4

This leads to an output characteristic equation for the linear region, which is

Equation 3.5

The derivation leading to (3.4) and (3.5) is given in Unit 3.4. The linear-region relation, (3.5), is applicable for V_DS up to V_DS = V_effn, which is the boundary of the linear and active regions. The active-region equation is then obtained by substituting into (3.5), V_DS = V_effn, giving

Equation 3.6

This active-region current corresponds to the zero-slope ideal curve in Fig. 3.3. As discussed in Unit 3.1, the drain current is not actually constant in the active region (in the same manner as for a BJT), due to the fact that the physical length of the channel is reduced for increasing V_DS beyond V_DS = V_effn. The reduction in the channel length has the effect of slightly reducing the resistance of the channel. This is taken into account using the fact that k_n ∝ 1/L, from (3.3), where L is the effective physical length between the source and drain regions. For V_DS > V_effn, a reduced length L′ = L(1 – λ_nV_DS) is defined which leads to a new effective ,

Equation 3.7

where λ_n is the SPICE channel-length modulation parameter (Lambda). Substituting for k_n in (3.6) produces

Equation 3.8

(Note: A preferred form would be I_D = k_n V_effn²[1 + λ_n (V_DS – V_effn)] because the channel-length effect only begins for V_DS > V_effn and k_n could be defined properly for effective length L at V_DS = V_effn. Level 1 SPICE uses (3.8).)

Level 1 SPICE also applies this channel-length reduction factor to the equation in the linear region, (3.5). To match the linear-region equation to the active-region equation, (3.5) becomes, at the edge of the active – linear regions,

Equation 3.9

and, in general

Equation 3.10

[Again, the fact that the channel length is not reduced with the transistor in the linear region would suggest the use of (3.9) throughout the linear region. Level 1 SPICE uses (3.8) and (3.10).]

In general, V_tn is a function of the source-body voltage, V_SB. We assume for the moment that V_SB = 0. This applies, for example, to the common-source circuit in Fig. 3.2, since the body will always be at zero volts, and the source in this case is grounded as well. For this case, V_tn = V_tno, as used above. In laboratory projects we measure the output characteristic from which parameter λ_n can be obtained. This is based on (3.8). The I – V slope in the active region is

Equation 3.11

From the data measured, a straight-line curve fit determines the slope and the zero V_DS intercept (I_D at V_DS = 0). These are used in (3.11) to obtain λ_n from λ_n = slope/intercept. The intercept is the extension of the active region of Fig. 3.3 (dashed line) to the I_D axis.

When applying the equations of this development to the PMOS, the voltage between the gate and source is defined as positive with respect to the source, that is, V_SG. To be consistent, the threshold voltage for the PMOS, V_tp, is also positive. In the SPICE model, however, the threshold voltage is assigned negative because positive is taken for both types of devices with respect to the gate (V_GS is negative for the PMOS), and the threshold voltage for the PMOS is negative.

The transfer characteristic is obtained by holding V_DS constant and varying V_GS. In the MOSFET parameter-determination experiments of Projects 3 and 4, we plot V_GS versus for the transistor biased into the active region. The equation is

Equation 3.12

where is (3.7)

The slope in (3.12) is and the zero intercept is expected to be V_tno. LabVIEW obtains the slope and intercept from a straight-line fit to the data. The measured transfer characteristic thus yields the two parameters and V_tno.

In Project 4, parameter λ_n is obtained from finding at two different V_DS values. This is based on

Equation 3.13

where the values are measured and λ_n is the only unknown.