Components

C₁ = C₂

f_3dBhi = 50f_3dBlo

R_s ≈ R_G/50

f_3dBlo = 5 Hz (approximately)

Typical C₁ ≈ 0.5 μF

Procedure

• Configure the circuit for the low-end measurement and f_3dBlo. Install C₁ and do not install C₂. Run VI_05.vi to obtain f_3dBlo. Obtain a Log of the Front Panel to save the results. To obtain a Log, go through menu sequence Operate>>Data Logging>>Log. To retrieve data: Operate>>Data Logging>>Retrieve.
  
  
• An example of retrieving a Log using VI_01.vi is shown here. Note that at the first Data Logging, you will be asked to name a Data Log file. Select any name and Click Save, to install Log File in the Project folder.
  
  

  

• Now move the capacitor C₂ = C₁ to the C₂ location and install a large capacitor, C_1new, in place of C₁, which satisfies C_1new >> C₂ (e.g., C_1new = 47 μF). Note that the source side of the capacitor (connected to R_s) is more negative than the output side (Chan0_in). Run VI_05.vi to obtain f_3dBhi. Default and save the Front Panel. Note that when reopening the VI, the Front Panel will contain the information last defaulted from this f3dBhi measurement. The first measurement is in the data Log. Repeating, to retrieve the information from the data Log, go through menu sequence Operate>>Data Logging>>Retrieve. To then go back to the defaulted Front Panel, click OK and go through Operate>>Reinitialize All to Default Values.
  
  
• Note that if C₂ = C₁ are actually both in the circuit at the same time, the output in the plateau region is 1/2 as large (Exercise 1). This configuration is not implemented here. The use of C₂ = C₁ is only for convenience and f_3dBlo << f_3dBhi is satisfied with R_s << R_G.