Components NPN

R_Bp ≈ R_Bn.

If slightly different, use R_Bp > R_Bn.

Design I_C = 1mA.

Procedure

• SetVCE2.vi ramps VBB downward from the maximum,VBB(init) = VCC(init). Thus, initially, the npn will be in saturation and V_CE will be very approximately 100 mV. The first check is for one point, maximum VBB = VCC = 10 V. The initial goal is verify that the npn is in saturation and that the current is greater than 1 mA for VCC = 10 V.
  
  
• Connect Circuit C5. Note that the bottom of RBp is now ground and Chan1_out moves to the bottom of RBn. Also, the collectors are connected together and Chan1_in moves to the base of the npn. Move the plus side of Chan2_in and the top of REp to Chan0_out.
  
  
• Set in resistor values in SetVCE2.vi. Verify that VBB(init) = 10 V and VCC(init) = 10 V. Set the Run Mode switch to One VCC (logic 1). Run the VI. Verify that IC>1 mA and and that VCE is 50 to 300 mV (in saturation).
  
  
• SetVCE2.vi calculates the V_CE operating point (bias voltage) as (V_CC – V_REp)/ 2 for any V_CC (optimum signal swing magnitude). When the Run Mode is set to Set VCE, the execution of the VI halts when this level of V_CE is reached.

  

  
  
  
• Set the Run Mode switch to Set VCE. Run the VI. Verify that the execution halts when VCE is about equal to VCE(V)Op.Pt. Note that in the example, IC = 1.14 mA for VCC = 10 V and VBB = 9.02 V. Verify that the final VCE is close to VCE(V)Op.Pt. Default the Front Panel to save the values of RBn and REp.
  
  
• SetIC.vi runs SetVCE2.vi as a subVI. It ramps VCC downward to find the VCC corresponding to the design IC = 1 mA. Open SetIC.vi and have SetVCE2.vi open as well. SetIC.vi will be a subVI in the gain measurement VI. Run the VI to verify that the VI can determine the VCC corresponding to IC = 1 mA. In the example, VCC has been ramped down to 9.0 V and VBB is now down to 8.1 V. The routine will occur automatically in the execution of the gain measurement VI.