10.1. DC (Bias) Circuit
The bias circuit is critical in terms of getting the dc output voltage at a value near the project design value of VO = VDD/2 (for maximum output magnitude and linearity). The relation, from the dc circuit analysis, for obtaining this condition is based on ID1 = ID2. This is, in terms of the transistor characteristic equations, (3.8),
Equation 10.1
Note that the source-gate voltage of M2 is referenced to M3. A certain combination of VGS1 and VSS will satisfy Vo = VDD/2. In the project on the amplifier, a LabVIEW VI sends out a VG1 = VGS1 to set up a given ID1 = ID2 and then adjusts VSS to obtain the desired bias output voltage.
Figure 10.2 shows a SPICE plot of the current for the PMOS and NMOS transistors as a function of VDS1. The source – drain voltage for the PMOS is VSD2 = VDD – VDS1. Both transistors have a specific gate – source voltage. The solution for the output voltage for this case is about 3 V. A slight decrease in VGS1 or a slight increase in VSG2 is required to bring VDS1 to 5 V, the design result in this example. The increase in VSG2 would be implemented by making VSS more negative to increase the reference current. The steeper slope in the active region of the PMOS device is consistent with λp > λn, as in the project amplifier.
Figure 10.2. Plot of driver and load transistor output characteristics on common voltage scale. Since ID1 = IDn = ID2 = IDp, VDS1 = VO is where currents intersect. The current from the current source load needs, in this example, to be slightly increased to set VDS1 = VO, with VDD = 5V.
