Start in the Mathcad file Project07.mcd to compute circuit component values as follows:
We will design for a selected IDmax at Chan0_outmax = 10 V with VDSmin = 1V. Select your IDmax in the range 100 μA < IDmax < 500 μA.
Make RG1 = RG2 ≈ 100 kΩ. Thus, the gate voltage is
VG = Chan0_outmax/2.
Select the circuit source resistor, RS, to satisfy VG = VGS (IDmax) + IDmaxRs. VGS (IDmax) can be calculated using previously measured parameters or obtained graphically from, for example, NMOSparam.vi from Project 4.
After acquiring a real RS (which is close to the calculated value), calculate an actual, new IDmax using the same equation in reverse with the real RS. Neglect the change in VGS.
We will select RD to set the condition of VDSmin = 1 V (at Chan0_outmax) from RD = (VDD – VDSmin)/IDmax– Rs. (Use actual, new IDmax.)
Procedure (Measurement)
Install your value of RS in CSAMPBIAS.vi (for current sensing). With VDD = 10 V (VDDmax), run the VI to verify the design. VDSmin can be significantly different from design 1 V due to parameter variation. For example, 1 < VDSmin < 1.5 V is satisfactory, where the low limitation is based on VDSmin > Veffn. This is the requirement to be in the active region. In the example, the design drain current is IDmax = 300 μA.
Verify that as VDD is reduced, ID decreases and VDS increases. Check VDD = 4 V, the minimum in the sweep for parameter measurement of the next part. Verify that at the minimum VDD, VDS > ID·RD Obtain a log for Chan0_out = 10V.
Reduce VDD from the maximum VDD = 10 V and determine, approximately, the value between 4V < VDD < 10V that corresponds to VDS ≈ IDRD. This is the operating point (bias) condition for the amplifier gain measurement. This will be found automatically in the gain measurement VI.
