3.1. Physical Description of the MOSFET

A diagrammatic NMOS is shown in Fig. 3.1. The device consists of a three-layer structure of metal–oxide–semiconductor (MOS). A two-terminal MOS structure (connections to metal and semiconductor) is essentially a parallel-plate capacitor. In the same manner as for a normal capacitor, when a positive gate voltage, V_G, is applied with respect to the p-type body (for NMOS) [i.e., with respect to the metal contact on the underside of the p-type semiconductor body (or substrate)], negative charges are induced under the oxide layer in the semiconductor. When V_G (with respect to the semiconductor body) exceeds the threshold voltage, V_tno, a channel of free-carrier electrons forms under the oxide; that is, the onset of the channel occurs when V_G = V_tno. The substrate is n type for the PMOS and the channel is made up of free-carrier holes.

An n-channel MOSFET device is then completed by fabricating n regions, source and gate, for contacting the channel on both ends of the channel. For V_G < V_tno [Fig. 3.1(a)] there is no channel under the oxide, and the two n regions are isolated pn junctions. When V_G > V_tno and source voltage, V_S, and drain voltage, V_D, are both zero (all with respect to the body) [Fig. 3.1(b)] a uniform-thickness n-type channel exists along the length of the oxide layer and the source and drain regions are connected by the channel. Thus, the channel is a voltage-controlled resistor where the two ends of the resistor are at the source and drain and the control voltage is applied at the gate.

In electronic circuit applications, the terminal voltages are referred to the source; gate and drain voltages are designated as V_GS and V_DS (NMOS). In analog circuits, V_GS > V_tno (in order for a channel to exist), V_DS is positive, and a drain current flows through the channel and out by way of the source (and the gate current is zero). On the drain end of the channel, the voltage across the oxide layer is V_GD = V_GS – V_DS. The channel at the drain end just shuts off when V_GD = V_tno. V_DSsat = V_GS – V_tno [Fig. 3.1(c)] is defined for this condition as the saturation voltage. The transistor is referred to as in the linear (or triode) region or active region for V_DS < V_DSsat and V_DS > V_DSsat, respectively.

For V_DS > V_DSsat (active mode of operation), the channel length decreases from L to L′ as the reverse-biased depletion region of the drain pn junction increases along the channel (along the oxide – semiconductor interface) [Fig. 3.1(d)]. The increment V_DS – V_DSsat drops across the depletion region of the drain pn junction. In long-channel devices, the reduction of channel length is relatively small compared to the channel length. In this case, the length is roughly a constant and the channel resistance, for a given V_GS, is independent of V_DS.

From a circuit point of view, for V_DS >> V_DSsat, by Ohm’s law,

Equation 3.1

where R_chan(V_GS) is the resistance of the channel and is a function of V_GS. Assuming that L′ ≈ L, for a given V_GS, R_chan(V_GS), and thus I_D, is approximately a constant for V_DS ≥ V_DSsat. Thus, the drain, in circuit terms, appears like a current source. In many modern MOSFET devices, this is only marginally valid. In the following, the definition V_effn ≡ V_DSsat = V_GS – V_tno will be used. (The subscript is an abbreviation for effective.) The PMOS has a counterpart, V_effp ≡ V_SDsat = V_SG – V_tpo. V_effp is a frequently recurring term in device and circuit analytical formulations.