Instruction Set and Assembly Language Programming 189
Nibbles: 3 Cycles: 4 Flags: none
3210
1110
3210
1011
3210
aaaa
WAP Write from accumulator to port address (one instruction).
Description: Content of accumulator is written to the addressed port. No ags are affected.
Syntax: WAP addr(4)
Nibbles: 3 Cycles: 4 Flags: none
3210
1110
3210
1100
3210
aaaa
SRB Select alternate register bank (one instruction bank)
Description: Select the other register bank. Presently selected bank becomes inactive. No ags are
affected.
Syntax: SRB
Nibbles: 2 Cycles: 2 Flags: none
3210
1001
3210
1001
EXA Exchange accumulator (one instruction)
Description: Interchange between current and passive accumulators. No other registers affected.
Syntax: EXA
Nibbles: 2 Cycles: 2 Flags: none
3210
1001
3210
0110
EXF Exchange ag registers (one instruction)
Description: Interchange between current and passive ag registers. No other registers affected.
Syntax: EXF
Nibbles: 2 Cycles: 2 Flags: none
3210
1001
3210
1010
EXR Exchange with register (seven instructions)
Description: Interchange between accumulator and indicated register (except A) No ags are affected in
any case except exchange with F register.
Syntax: EXR V
Nibbles: 2 Cycles: 2 Flags: none
3210
0101
3210
0rr r
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190 Computer Architecture and Organization
Arithmetic Instructions
ADR Add accumulator with carry and register (eight instructions)
Description: Content of accumulator is added with content of indicated register and content of carry
ag. Result in accumulator. Both carry and zero ags are affected.
Syntax: ADR W
Nibbles: 2 Cycles: 2 Flags: C, Z
3210
0101
3210
1rr r
ACI Add immediate with carry with accumulator (one instruction)
Description: The immediate data and content of carry ag is added with accumulator. Result in accumu-
lator. Both carry and zero ags are affected.
Syntax: ACI data(4)
Nibbles: 3 Cycles: 3 Flags: C, Z
3210
1110
3210
1101
3210
dddd
IRO Increment register by one (seven instruction)
Description: The content of indicated register is incremented by one. All seven registers except ag
register may be addressed. Both carry and zero ags are affected.
Syntax: IRO X
Nibbles: 2 Cycles: 2 Flags: C, Z
3210
0110
3210
0rr r
DRO Decrement register by one (seven instructions)
Description: The content of indicated register is decremented by one. All seven registers except ag
register may be addressed. Both carry and zero ags are affected.
Syntax: DRO A
Nibbles: 2 Cycles: 2 Flags: C, Z
3210
0110
3210
1rr r
Logical Instructions
RLC Rotate accumulator left through carry (one instruction)
Description: Bit 7 of accumulator is shifted to carry ag. Old content of carry ag shifted to bit 0 of
accumulator. Other bits of accumulator shifted left one bit. Only carry ag is affected.
Syntax: RLC
Nibbles: 2 Cycles: 2 Flags: C
3210
1001
3210
1011
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Instruction Set and Assembly Language Programming 191
RRC Rotate accumulator right through carry (one instruction)
Description: Bit 0 of accumulator is shifted to carry ag. Old content of carry ag shifted to bit 7 of
accumulator. Other bits of accumulator shifted right one bit. Only carry ag is affected.
Syntax: RRC
Nibbles: 2 Cycles: 2 Flags: C
3210
1001
3210
1100
RL Rotate accumulator circular left (one instruction)
Description: All bits of accumulator shifted one bit left. Old bit 7 becomes bit 0. No ags are affected.
Syntax: RL
Nibbles: 2 Cycles: 2 Flags: none
3210
1001
3210
1101
RR Rotate accumulator circular right (one instruction)
Description: All bits of accumulator shifted one bit right. Old bit 0 becomes bit 7. No ags are affected.
Syntax: RR
Nibbles: 2 Cycles: 2 Flags: none
3210
1001
3210
1110
LAR Logically AND accumulator with register (eight instructions)
Description: Content of indicated register is logically ANDed with content of accumulator. Result in
accumulator. Both carry and zero ags are affected.
Syntax: LAR W
Nibbles: 2 Cycles: 2 Flags: C, Z
3210
0111
3210
0rr r
LAI Logically AND immediate data with accumulator (one instruction)
Description: Content of accumulator is logically ANDed with immediate data. Result in accumulator.
Both carry and zero ags are affected.
Syntax: LAI data(4)
Nibbles: 3 Cycles: 3 Flags: C, Z
3210
1110
3210
1110
3210
dddd
LOR Logically OR accumulator with register (eight instructions)
Description: Content of indicated register is logically ORed with content of accumulator. Result in
accumulator. Both carry and zero ags are affected.
Syntax: LOR X
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192 Computer Architecture and Organization
Nibbles: 2 Cycles: 2 Flags: C, Z
3210
0111
3210
1rr r
LOI Logically OR immediate data with accumulator (one instruction)
Description: Content of accumulator is logically ORed with immediate data. Result in accumulator.
Both carry and zero ags are affected.
Syntax: LOI data(4)
Nibbles: 3 Cycles: 3 Flags: C, Z
3210
1110
3210
1111
3210
dddd
CAI Complement register (eight instructions)
Description: Content of indicated register is complemented. Result is register itself. No ags are affected
unless ag register is complemented.
Syntax: CAI Y
Nibbles: 2 Cycles: 2 Flags: none
3210
1000
3210
0rr r
CCI Complement carry ag (one instruction)
Description: Content of carry ag is complemented. Result in carry ag. Only carry ag is affected.
Syntax: CCI
Nibbles: 2 Cycles: 2 Flags: C
3210
1001
3210
0111
CCF Clear carry ag (one instruction)
Description: The carry ag is reset to 0. No other ag is affected except carry ag.
Syntax: CCF
Nibbles: 2 Cycles: 2 Flags: C
3210
1001
3210
1000
Program Branching Instructions
JCS Jump if carry is set (one instruction)
Description: Control branches to indicated address if carry ag is set. Otherwise execution proceeds
sequentially. No ags are affected.
Syntax: JCS addr(12)
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Instruction Set and Assembly Language Programming 193
Nibbles: 5 Cycles: 6 Flags: none
3
MSN LSN
210
1111
3210
1100
3210
aaaa
3210
aaaa
3210
aaaa
JZS Jump if zero (one instruction)
Description: Control branches to indicated address if zero ag is set. Otherwise execution proceeds
sequentially. No ags are affected.
Syntax: JZS addr(12)
Nibbles: 5 Cycles: 6 Flags: none
3
MSN LSN
210
1111
3210
1101
3210
aaaa
3210
aaaa
3210
aaaa
JUN Unconditional jump (one instruction)
Description: Control branches to the indicated address.
Syntax: JUN addr(12)
Nibbles: 5 Cycles: 6 Flags: none
3
MSN LSN
210
1111
3210
1110
3210
aaaa
3210
aaaa
3210
aaaa
CLL Call a subroutine (one instruction)
Description: Control is transferred to the indicated address after saving the return address on stack top.
No ags are affected.
Syntax: CLL addr(12)
Nibbles: 5 Cycles: 9 Flags: none
3
MSN LSN
210
1111
3210
1111
3210
aaaa
3210
aaaa
3210
aaaa
RTN return from subroutine (one instruction)
Description: Program counter is loaded from stack top. No ags are affected.
Syntax: RTN
Nibbles: 2 Cycles: 5 Flags: none
3210
1001
3210
1111
Opcode Design
Format and elds are two important aspects in opcode design. In this case, all 5-nibble instructions
have the rst nibble of 1111, while all 3-nibble instructions have the rst nibble of 1110. If the rst
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