The Sleep State

Refer to Figure 27-5 on page 693. The processor can only enter the Sleep state from the Stop Grant state. This occurs when the chipset asserts the SLP# (Sleep) signal to the processor while the processor is in the Stop Grant state. Upon entering the Sleep state, the processor powers off much of its logic, including that necessary for:

• Snooping memory accesses initiated by other agents on the FSB.

• Latching interrupt events.

Figure 27-5. The Sleep State

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The Sleep state has the following characteristics:

• The processor maintains the contents of its registers and caches.

• The processor's PLL (Phase Locked Loop) continues to run.

• All internal clocks are stopped. This stops CMOS input receivers from switching, thereby diminishing power consumption.

• An assertion of the SLP# pin is not recognized during the Normal or AutoHalt states.

• Snoop events that occur on the FSB while the processor is in the Sleep state or while the processor is transitioning in or out of the Sleep state will result in unpredictable behavior.

• No transitions or assertions of signals (with the exception of SLP# or RESET#) are allowed on the FSB while the processor is in the Sleep state. Any transitions on any input signal before the processor has returned to the Stop Grant state will result in unpredictable behavior.

• If RESET# is asserted while the processor is in the Sleep state, the processor is initialized and immediately transitions to the Normal state (without passing through the Stop Grant state). The SLP# and STPCLK# signals must be deasserted immediately after RESET# is asserted.

• The SLP# pin has a minimum assertion period of one BCLK.