The P6 Processor Core

The P6 processor core consists of (the pipeline stages are shown in Figure 23-2 on page 546):

• The front-end logic that, guided by the processor's Branch Prediction logic, fetches IA32 instructions from memory and stages them in the L1 Code Cache to be supplied to the processor's instruction pipeline.

• The decode logic that decodes the IA32 instructions that comprise the program into a series of primitive, fixed-length instruction referred to as μops (micro-ops).

• The μop pipeline stages that perform the following functions:

  - The μop Queue stage that accepts μops from the decoders.

  - The RAT (Register Alias Table) stage that allocates physical registers to be utilized in lieu of the GPRs.

  - The ROB stage wherein the μops are placed in the ReOrder Buffer until they complete execution and are retired.

  - The Dispatch stage wherein the μops are dispatched for execution.

  - The Execute stage.

  - The Retirement stages.

Figure 23-2. The P6 μop Pipelines Stages

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