The Spurious Interrupt Vector
The Problem
Assume that an interrupt is detected on the LINT0 input and, as a result, the Local APIC generates an interrupt to the processor. Also assume that, at this moment, the processor may raise its task priority (see “Task and Processor Priority” on page 1551) to be >= the level of the interrupt for which the processor is being interrupted. In the interval between the dispatch of the interrupt to the processor core and the core requesting the vector from the Local APIC, software may have masked that particular interrupt. What vector will the Local APIC supply to the processor core?
The Solution
In the scenario just described, the Local APIC delivers a spurious interrupt vector to the processor core. Refer to Figure 61-35 on page 1593. The Local APIC supplies the vector from its Spurious Interrupt Vector register.
In the Pentium® and P6 processor families, bits [7:4] are programmable by software and bits [3:0] are hardwired to ones. Software writes to bits 0 through 3 have no effect.
In the Pentium® 4 processor family, bits [7:0] are programmable by software.
Figure 61-35. The Local APIC's Spurious Interrupt Vector Register
This register is initialized to 000000FFh. Since no bit is set in the Local APIC's ISR when the spurious interrupt vector is returned to the processor, the spurious interrupt handler does not need to write to the Local APIC's EOI register. Typically, the handler would consist solely of an IRET instruction to return to the interrupted program.
Additional Spurious Vector Register Features
In addition to the Spurious Vector field, the Spurious Interrupt Vector register also contains the following bit fields:
If the APIC Global Enable/Disable bit in the IA32_APIC_BASE MSR has not been cleared to zero, software can disable the Local APIC by clearing the APIC Software Enable/Disable bit in the Spurious Vector register (see Figure 61-35 on page 1593), and can re-enable the Local APIC by setting this bit back to one. The default state of this bit after reset is 0 (the Local APIC is disabled).
The Focus Processor Check bit. Selects whether Focus Processor Checking is enabled (0) or disabled (1) when using the Lowest-Priority Delivery Mode. This bit is reserved in Pentium® 4 family processors and must be cleared to 0. In P6 and Pentium® family processors, if a focus processor exists, it may accept an interrupt that uses Lowest-Priority Delivery Mode regardless of the processor's current priority.