A Task Switch Causes an EFlags Update

While executing a DOS task in VM86 mode, a task switch results when an interrupt or exception selects an entry in the Protected Mode IDT that contains a Task Gate. A classic example would be the hardware interrupt generated by the timeslice timer. This interrupt typically selects an IDT entry that contains a Task Gate and a task switch occurs.

When the DOS task is suspended, the current contents of most of the processor's registers are saved in the DOS task's TSS. The copy of the EFlags register saved in the TSS has EFlags[VM] set to one. The processor's registers (including EFlags) are then loaded from the new task's TSS.

• If the new task is also a DOS task, the copy of EFlags read from the new task's TSS also has EFlags[VM] set to one and the processor remains in VM86 mode when the new task starts.

• If the new task is not a DOS task, the copy of EFlags read from the new task's TSS has a zero in EFlags[VM], causing the processor to exit VM86 mode when the new task starts (or resumes).