Memory Transaction Snooping

The Snoop's Effects on Processor Caches

When a memory transaction is snooped, the snoop result affects both the Request Agent and the Snoop Agents. There are a number of possible cases. The type of memory transaction, whether or not other caches have a copy of the line, and the state of the line(s) in other caches all have an effect. In addition, sometimes the length of the data transfer has an effect. Table 50-2 on page 1235 defines the scenarios and the results (assuming that the Request Agent is a processor).

Table 50-2. The Effects of Snoop
Transaction SnoopedSnoop ResultEffects of Snoop Result
Memory ReadMiss on all cachesThe data is supplied by memory:

  • If it is a Trace Cache line fill, the line is placed in the Trace Cache in the S state (the Trace Cache is SI, not MESI) and in the E state in the L2 Cache.

  • If it is an L1 Data Cache line fill, the line is placed in the L2 Cache in the E state and the L1 Data Cache in the S state.

Hit on E or S line in one or more cachesThe data is supplied by memory:

  • If it is a Trace Cache line fill, the line is placed in the Trace Cache and L2 Caches in the S state.

  • If it is an L1 Data Cache line fill, the line is placed in the L2 and the L1 Data Cache in the S state. If a Snoop Agent had a copy of the line in the E state, it changes it to the S state.

Hit on M line in one cacheThe operation started as a read from memory, but this changes it to a read of the M line from the Snoop Agent's cache. From the memory controller's standpoint, the read has turned into an implicit writeback of the M line to memory. The memory controller issues an implicit writeback response to the Request Agent in the Response Phase and accepts the line from the Snoop Agent during the Data Phase. The Snoop Agent changes its copy from the M to the S state. The Request Agent may have requested less than a line, but a full line is returned in toggle mode order, critical qword first. The Request Agent takes the data it requested and ignores the rest. If it requested the whole line, the line is placed in the L2 and Trace Cache or Data Cache in the S state.
Memory WriteMiss on all cachesThe data is written to memory. There is no effect on the caches.
Hit on E or S line in one or more cachesThe Snoopers indicate a miss. The transaction invalidates copies of the line in other caches (because the processors don't have the ability to snarf data being written to memory by other agents).
Hit on M line in one cache

Case 1: Writing less than a line. The Memory Write is being performed by a device other than a processor. The memory controller accepts the write data from the Request Agent, and then accepts the implicit writeback of the full line from the Snoop Agent's cache. The memory controller than merges the write data into the writeback line and writes the resultant line into memory. The Snoop Agent invalidates its copy of the line.

Case 2: Writing a full line. The Memory Write is being performed by a device other than a processor. The memory controller accepts the write data from the Request Agent, and then asserts TRDY# to the Snoop Agent to indicate its readiness to accept the implicit writeback of the full line from the Snoop Agent's cache. The Snoop Agent can respond in one of two ways:

  • If it doesn't check the length of the write data, it asserts DBSY# and uses the data bus to supply the modified line to the memory controller. The memory controller merges the write data into the writeback line, and then writes the resultant line into memory. Alternately, the memory controller could discard the modified line.

  • Alternatively, it could note that the Request Agent is writing a full line and decide that it won't send the modified line to the Response Agent (i.e., the memory controller). This is indicated by not asserting DBSY# in response to the assertion of TRDY#. The memory controller writes the line received from the Request Agent into memory.

In either case, the Snoop Agent invalidates its copy of the line.
Memory Read and Invalidate for 64 bytesMiss on all cachesThe data is supplied by memory and is placed in the L1 Data Cache in the S state. The transaction is basically a Read With Intent To Modify (RWITM):

  • If the processor immediately modified one or more locations within the line (e.g., the update of a semaphore), the line is now in the M state in the L2 Cache.

  • If the processor chooses not to update any locations in the line (e.g., the semaphore tested is already set), the line is placed in the E state in the L2 Cache.

Hit on E or S line in one or more cachesThe Snoopers indicate a miss. The data is supplied by memory and is placed in the L1 Data Cache in the S state. Copies of the line in the other caches are invalidated. The transaction is basically a Read With Intent To Modify (RWITM);

  • If the programmer immediately modified one or more locations within the line (e.g., the update of a semaphore), the line is now in the M state in the L2 Cache.

  • If the programmer chooses not to update any locations in the line (e.g., the semaphore tested is already set), the line is placed in the E state in the L2 Cache.

Hit on M line in one cacheThe data is supplied to the Request Agent and to the Response Agent (i.e., the memory controller) from the modified line in the Snoop Agent's cache. The Snoop Agent invalidates its copy of the line. The Response Agent (i.e., the memory controller) may or may not write the line into memory. Since the line was read with the intent to modify it once it is placed in the L1 Data Cache, the memory controller designer may choose not to waste memory bandwidth:

  • If the programmer immediately modified one or more locations within the line (e.g., the update of a semaphore), the line is now in the M state in the L2 Cache and in the S state in the L1 Data Cache.

  • If the programmer chooses not to update any locations in the line (e.g., the semaphore tested is already set), the line is placed in the E state in the L2 Cache and in the S state in the L1 Data Cache.

Memory Read and Invalidate for 0 bytesNo other processor has a copy of the line in any stateIf no other processor has a copy of the line, that means this initiating processor has an E copy of the line! That being the case, the processor would not initiate a 0-byte MRI to kill the line in the caches of other processors. This won't happen.
Hit on an E line in the cache of one other processorIf another processor has an E copy of the line, than that means the initiating processor doesn't have copy. That being the case, the processor would be performing a Memory Read and Invalidate for a full line, not 0 bytes. This won't happen.
Hit on S line in the caches of one or more other processorsThe processor performing the transaction has a copy in the S state. The transaction kills the line in the other processors that have it in the S state. The snoopers indicate a miss:

  • If the initiating processor immediately modified one or more locations within the line (e.g., the update of a semaphore), the line is now in the M state in the L2 Cache and in the S state in the L1 Data Cache.

  • If the initiating processor chooses not to update any locations in the line (e.g., the semaphore tested is already set), the line is placed in the E state in the L2 Cache and in the S state in the L1 Data Cache.

Hit on M line in one processorIf another processor has a copy of the line in the M state, then the processor performing the transaction doesn't have a copy. It would therefore have a miss on its Data Cache and would perform a Memory Read and Invalidate for a full line, not 0 bytes. This won't happen.

Self-Snooping

A Pentium® 4 processor snoops all memory transactions that occur on the FSB, including those initiated by itself. This is true even in a single-processor system. For an example of self-snooping, refer to “Self-Modifying Code and the P6” on page 281 on the CD.

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