386 Power-Up State

When the system is first powered up, the Reset signal is asserted until the power supply output voltages have stabilized. Reset prevents the system from performing any actions until the power is stable. In addition, it presets many devices, including the processor, to a known state so that they always begin operation in the same manner.

The assertion of reset on power-up forces the values indicated in Table 5-4 on page 67 into the registers listed (see Figure 5-19 on page 67). As a result, the processor always starts up in Real Mode with Paging and interrupt recognition disabled. When reset is deasserted, the processor fetches its first instruction from memory.

Table 5-4. 386 Registers after Reset
RegisterState After Reset
CSContains F000h. As a result, the Code Segment starts at memory location 000F0000h. Actually, it starts at FFFF0000h (refer to the section entitled “Initial Memory Reads” on page 69). The invisible part of the CS register (referred to as the CS cache register) is loaded with values that define the Code Segment as having the following characteristics:

  • It starts at memory location FFFF0000h.

  • Its length = 0FFFFh (64KB).

  • The segment is present in memory.

  • It's a read/write segment.

  • The segment has been accessed.

A description of the segment cache registers can be found in the section entitled “Segment Register—Selects Descriptor Table and Entry” on page 112.
EIPContains 0000FFF0h. The first instruction is fetched from location 0000FFF0h in the code segment (see the previous entry in this table) that starts at memory location FFFF0000h (in other words, location FFFFFFF0h).
DS, ES, FS, GSAll of the data segment registers contain 0000h. The invisible part of the data segment registers (referred to as cache registers) are loaded with values that define each of the data segments as having the following characteristics:

  • It starts at memory location 00000000h.

  • Its length = 0FFFFh (64KB).

  • The segment is present in memory.

  • It's a read/write segment.

  • The segment has been accessed.

A description of the segment cache registers can be found in the section entitled “Segment Register—Selects Descriptor Table and Entry” on page 112.
SSThe Stack Segment register contains 0000h. The invisible part of the Stack Segment register (referred to as the SS cache register) is loaded with values that define the Stack Segment as having the following characteristics:

  • It starts at memory location 00000000h.

  • Its length = 0FFFFh (64KB).

  • The segment is present in memory.

  • It's a read/write segment.

  • The segment has been accessed.

  • It's an expand-up stack segment.

A description of the segment cache registers can be found in the section entitled “Segment Register—Selects Descriptor Table and Entry” on page 112.
CR0Contains 00000010h. As a result, the processor exhibits the following characteristics:

  • It's in Real Mode CR0[PE] = 0).

  • The processor is not aware (CR0[MP] = 0) of the presence of an external FPU (i.e., a 287 or 387 FPU).

  • The processor will not emulate the FPU (CR0[EM] = 0).

  • Paging is disabled.

EFlagsContains 00000002h. As a result, the processor exhibits the following characteristics:

  • Single-step mode is disabled (EFlags[TF] = 0).

  • Recognition of external interrupts (detected on the on INTR input pin) is disabled (EFlags[IF] = 0).

  • String instructions auto-increment the memory address pointers in ESI and EDI (EFlags[DF] = 0).

  • The IOPL (IO Privilege Level) is set to zero (EFlags[IOPL] = 00b; this has no effect in Real Mode).

  • Debug fault checking is enabled after execution of an IRETD instruction (EFlags[RF] = 0).

  • Virtual 8086 mode is disabled (EFlags[VM] = 0).

CR2Contains a Page Fault Linear Address of 00000000h. This has no effect in Real Mode (because paging is disabled).
CR3Contains a Page Directory start address of 00000000h. This has no effect (because paging is disabled).
ESPContains 00000000h. The Top-of-Stack (TOS) is set to memory location zero (the same as the Stack Segment's base address).
Debug registersDR7 contains 00000400h, disabling the processor's breakpoint recognition logic.
IDTRThe IDTR contain 0000h. This defines the Interrupt Table as having the following characteristics:

  • It starts at memory location 00000000h.

  • Its length = 0FFFFh (64KB).

  • It is present in memory.

  • It is read/write accessible.


Figure 5-19. 386 Register Set


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