Task and Processor Priority

Introduction

The Local APIC uses two register values to determine in what order to dispatch user-defined interrupts to the processor's core:

• The Task Priority Register (TPR).

• The Processor Priority Register (PPR).

The TPR is written to by the OS while the PPR derives its contents from the TPR and, if a user-defined interrupt is currently being serviced, the priority of that interrupt. In order to determine the eligibility of a user-defined interrupt to interrupt the executing program or the currently executing user-defined interrupt handler, the Local APIC compares the user-defined interrupt's priority to the processor's priority. The following sections describe the TPR, the PPR and the eligibility test.

The Task Priority Register (TPR)

As described in “The Priority Amongst the User-Defined Interrupts” on page 1519, the user-defined interrupts (16 through 255) are divided into 15 classes with class 15 having the highest priority and class 1 having the lowest. Within each class, the numerically lowest-numbered interrupt has the lowest priority and the highest numbered has the highest priority.

When the OS instructs a processor to start executing a task, it also programs the Local APIC's Task Priority Register (TPR; see Figure 61-23 on page 1552) with a value that defines a threshold that must be exceeded by any user-defined interrupt that is received while the current task is executing.

The Processor Priority Register (PPR)

At a given moment in time, the TPR reflects the relative importance of the program currently being executed (from the OS's point of view). Consider the following scenario:

• The TPR contains the value 93h, indicating that the currently executing program will not be interrupted by any user-defined interrupt that is <= 93h.

• A user-defined interrupt of A2h is received and is dispatched to the processor core for execution (because it is > 93h).

• A new value of B9h is written into the TPR (indicating that the priority of the currently executing program is B9h). The priority of the user-defined interrupt that is still in the process of being serviced is A2h.

The PPR (see Figure 61-24 on page 1553) is a read-only register and its content is automatically updated by the processor whenever a new value is written into the TPR, or when a user-defined interrupt is dispatched to the processor core.

The PPR value is updated as follows:

IF TPR's Class >= Class of the in-service interrupt
 THEN
      Set Processor Priority = Task Priority
 ELSE
      Set PPR Class = Class of the in-service interrupt
      Set PPR SubClass = 0

Stated another way:

• If the class (i.e., the priority of) of the executing program is > the class of (i.e., the priority of) the user-defined interrupt being serviced (or 0 if none is being serviced), then the processor's priority is set to the priority of the executing program.

• If the class of the executing program is <= the class of the user-defined interrupt being serviced (or 0 if none is being serviced), then the processor's priority is set to the priority of the user-defined interrupt being serviced.

The User-Defined Interrupt Eligibility Test

When a user-defined interrupt is received, the upper four bits of the user-defined interrupt vector identifies the class (i.e., the priority) of the interrupt. In order to be considered for dispatch to the processor core, the interrupt's class must meet or beat the value in the PPR's Processor Priority Class field:

It should be noted, however, that a number of different interrupts may be eligible to interrupt the current program. The order in which they will be dispatched to the processor core for servicing is decided based on their relative importance to each other (see Table 61-2 on page 1520).

As an example, assume that the PPR contains the value 000000A5h and that the following user-defined interrupts are received:

• User-defined interrupt F9h. This interrupt has a Class of Fh and is > the Class specified in the PPR (Ah). It therefore will be permitted to interrupt the currently executing task.

• User-defined interrupt A3h. This interrupt has a Class of Ah, the same as that specified in the PPR. However, it has a SubClass of 3 which is < the SubClass specified in the PPR. It therefore will not be permitted to interrupt the currently executing program.

• User-defined interrupt D2h. This interrupt has a Class of Dh and is > the Class specified in the PPR (Ah). It will therefore be permitted to interrupt the currently executing task.

• User-defined interrupt A5h. This interrupt has a Class of Ah, the same as that specified in the PPR. It has a SubClass of 5 which is = the SubClass specified in the PPR. It therefore will not be permitted to interrupt the currently executing program.

The order in which the eligible interrupts will be dispatched to the processor core is:

• Interrupt F9h is serviced first.

• Interrupt D2h is serviced second.

Interrupts A3h and A5h will not be serviced until the PPR contains a value that permits them to be serviced.