Basic Characteristics

The following is a list of the Pentium® II Xeon's basic characteristics (in no particular order):

• The Xeon was first introduced as a variant on the Pentium® II processor technology.

• It used the cartridge packaging, but it was a larger cartridge and used a different connector, referred to as the Slot 2 connector. This connector had more power and ground pins (because the larger, faster L2 Cache drew more power than the Pentium® II's L2 Cache).

• The Pentium® II Xeon's core speeds ranged from 400MHz to 450MHz.

• The electrical characteristics of the FSB signals were modified to accommodate a higher FSB speed. The GTL+ FSB electrical specification evolved into the AGTL+ specification.

• The Xeon used the same core as the Pentium® II.

• The FSB speed ran at a frequency of 100MHz (as did the later versions of the Pentium® II).

• The BSB ran at 100% of the processor's full core speed.

• The L2 Cache was available in three sizes: 512KB, 1MB and 2MB.

• The L2 was ECC protected.

• The L2 Cache could cache from the full 64GB of memory address space (versus 512MB or 4GB for the Pentium® II).

• The PSE-36 feature was added as an alternative to the PAE-36 feature.

• The SMBus was added and the processor incorporated a Processor Information ROM, a scratch EEPROM and a thermal diode that could all be read via the serial SMBus.

• The MP version implemented four Bus Request pins (BR[3:0]#) permitting the FSB arbitration scheme to support up to four processors (versus four for the Pro, two for the Pentium® II, and one for the Celeron).

• Due to the inability of processors to recognize FSB transactions during the Sleep power conservation state, multiprocessor Intel® Xeon systems are not allowed to simultaneously have one processor in the Sleep power conservation state while the other processors are in the Normal or the Stop Grant power conservation state (see “Pentium® II Power Management Features” on page 683).

• Xeons do not implement the Deep Sleep power conservation state.