The Roadmap

Table 33-1 on page 814 provides a brief description of the Pentium® 4 roadmap from its introduction and projecting into 2005. The reader should keep in mind that Intel®'s future roadmap is always subject to change, so don't consider the future roadmap as carved in bronze.

Table 33-1. The Pentium® 4 Roadmap
Code NameDateDescription
The Pentium® 4 Processor
Willamette11/20/00Released at 1.4/1.5GHz with the following major features (in no particular order and not a complete list):

  • SSE2 instructions added ability to perform matrix math on packed DP FP numbers, and ability to perform MMX operations on data packed into 128-bit XMM registers.

  • Completely re-designed core with 20 pipeline stages (see Figure 35-3 on page 846), versus 10 in the P6 processor family (see Figure 35-2 on page 845).

  • Improved branch prediction to avoid mispredictions whenever possible and the deep performance degradation that results from the pipeline flush.

  • The L1 Code Cache was redesigned to cache μops rather than legacy IA32 instructions. It is referred to as the Trace Cache (TC) and only caches μops corresponding to IA32 instructions along the predicted execution path.

  • The two integer execution units enhanced to complete the execution of an instruction in half a processor cycle (as opposed to one clock cycle in the P6 processors; referred to as double pumping the execution units). They are referred to as the Rapid Execution Engine.

  • The die also contains two FP units, one of which deals with x87 FP instructions, MMX and SSE-2 while the other manages FP moves and stores.

  • The cache line size was increased from 32 to 128 bytes.

  • The on-die L2 cache is 256KB in size.

  • The L2 Cache can deliver data in every clock cycle (versus the Coppermine L2 cache's ability to deliver in every other clock cycle).

  • It is based on the 0.18μm technology.

  • The FSB has a double-pumped Request Phase and a quad-pumped Data Phase.

  • The Error Phase has been eliminated.

  • Interrupts are delivered over the processor's FSB.

  • The 3-wire APIC bus has been eliminated.

  • This version did not implement the Hyper-Threading feature (code named Jackson).

Northwood01/07/02This model was released at 2 and 2.2GHz and had the following additional major features (in no particular order and not a complete list):

  • Based on 0.13 micron technology.

  • 512KB on-die L2 Cache.

Northwood B with HyperThreading11/14/02This model was released at 3.06GHz and had the following major features (in no particular order and not a complete list):

  • First desktop Pentium® 4 with Hyper-Threading.

Northwood with 800MHz FSB04/14/03This model was released at 3GHz and had the following major features (in no particular order and not a complete list):

  • This is the first IA32 processor with the quad-pumped, 800MHz FSB.

Pentium® 4 Extreme Edition (Gallatin)09/16/03This model was released at 3.2GHz and had the following major features (in no particular order and not a complete list):

  • Based on the Xeon MP's Gallatin core.

  • Quad-pumped, 800MHz FSB.

  • 512KB L2 Cache.

  • 2MB on-die L3 Cache.

Prescott02/01/04This model was released at 2.4, 2.8, 3.0, 3.2 and 3.4GHz and had the following major features (in no particular order and not a complete list):

  • The first IA32 processor based on 90nm (nanometer) technology.

  • Added the SSE3 instruction set (13 instructions).

  • Included a 2.8GHz model without Hyper-Threading and with a 533MHz, quad-pumped FSB.

  • 1MB L2 Cache.

  • 16KB L1 Data Cache.

  • Improved branch prediction.

  • Improved Data Prefetcher.

  • Two new instructions were added to improve thread synchronization when using Hyper-Threading.

  • The instruction pipeline was expanded from 20 to 31 stages.

TejasQ2 of 2005It is expected that this model will be released at 3.6GHz and eventually achieve 6GHz (or, as some believe, 9.2GHz). The following major features (in no particular order and not a complete list) are anticipated:

  • Base on 90nm technology.

  • Packaged in a 775 contact LGA (might be called Socket T). Processors could be snapped in and out of a system board using a waffle-iron like device.

  • Improved Hyper-Threading.

  • Eight new multimedia instructions.

  • 24KB L1 Data Cache.

  • Initial FSB speed of 800MHz FSB.

  • Eventual FSB speed of 1.066GHz.

Nehalem2005This processor is expected to have a completely new core design and is expected to be initially based on 90nm technology.
The Pentium® 4 Celeron Processor
Celeron Willamette05/15/01This model was released at 1.7GHz and has the following major features (in no particular order and not a complete list):

  • Based on the Willamette core.

  • On-die L2 cache is 128KB in size (versus 256KB on Willamette core).

  • Based on 0.18 micron technology.

  • 400MHz, quad-pumped FSB.

Celeron Northwood9/18/02This model was released at 2GHz and had the following major features (in no particular order and not a complete list):

  • Based on the Northwood core.

  • 128KB L2 Cache.

  • 400MHz, quad-pumped FSB.

Celeron PrescottQ2, 2004Expected to be released at 2.53, 2.66, 2.8 and 3.06GHz. The following major features (in no particular order and not a complete list) are anticipated:

  • 256KB on-die L2 Cache.

  • 533MHz, quad-pumped FSB.

The Pentium® 4 Xeon Processor
Foster DP05/21/01This model was released at 1.4, 1.5 and 1.7GHz and had the following major features (in no particular order and not a complete list):

  • Supported two processors on the FSB.

  • Did not implement Hyper-Threading.

Foster MP03/12/02This model was released at 1.4, 1.5 and 1.6GHz and had the following major features (in no particular order and not a complete list):

  • Supports up to four processors on the FSB.

  • 256KB on-die L2 Cache.

  • On-die 512KB or 1MB L3 Cache.

  • Did not implement Hyper-Threading.

Prestonia with Hyper-Threading02/25/02This model was released at 1.8, 2.0 and 2.2GHz and had the following major features (in no particular order and not a complete list):

  • Based on 0.13 micron technology.

  • The first IA32 processor to implement Hyper-Threading (formally code named Jackson).

Prestonia B11/18/02This model was released at 2.0, 2.4, 2.6 and 2.8GHz and had the following major features (in no particular order and not a complete list):

  • 533MHz, quad-pumped FSB.

  • Uses Socket 604 (previous Xeons used Socket 603).

GallatinþMP11/04/02This model was released at 1.5, 1.9 and 2GHz and had the following major features (in no particular order and not a complete list):

  • Based on 0.13 micron technology.

  • It's the successor to the Foster MP mode.

  • Integrated on-die L3 Cache (1MB or 2MB in size).

  • Implemented Hyper-Threading.

Prestonia with 1MB L307/14/03The first Xeon DP with an on-die 1MB L3 Cache.
Gallatin 4M02/29/04This model was released at 3GHz and had the following major features (in no particular order and not a complete list):

  • Xeon MP.

  • On-die 4MB L3 Cache.

  • Supports up to four processors on the FSB.

  • There is also a version with a 2MB on-die L3 Cache.

Nocona DPJune 28, 2004This processor is expected to have the following characteristics:

  • It is the first Intel® IA32 processor to implement the AMD64 extensions to the IA32 architecture. Intel® refers to this feature as IA32e, EMT64, and as the CT technology.

  • Based on 90nm technology.

  • A 3.2GHz clock rate.

  • Supports two processors on the FSB.

  • 800MHz, quad-pumped FSB.

  • 1MB on-die L2 Cache.

  • 2MB on-die L3 Cache.

  • Two new instructions will be added to improve thread synchronization when using Hyper-Threading.

Potomac MP1st half, 2005Up to 2/17/04, this was expected to be Nocona with the 64-bit extensions added in. On 2/17/04, however, Intel® announced that, starting with Nocona, all future Xeon products would incorporate the IA32e (EM64T) extensions. Will support up to eight processors.
JayhawkQ2, 2005Expected to be released at 4GHz. The following major features (in no particular order and not a complete list) are anticipated:

  • Based on 90nm technology.

  • 2MB on-die L3 Cache.

  • 800MHz, quad-pumped FSB.

The Mobile Pentium® 4 Processor
Banias03/12/03This processor is a member of P6 processor family and really shouldn't be in this chapter. It was included because so many people expect to find it here thinking that it's a Pentium® 4 derivative. Rather, it is based on the Pentium® III processor core. This model was released at 1.3, 1.4, 1.5 and 1.6GHz, is officially known as the Pentium® M processor (not to be confused with the Pentium® 4 M) and has the following major features (in no particular order and not a complete list):

  • Part of the Centrino chipset.

  • Based on the Pentium® III core (not that Intel® has never officially acknowledged this).

  • Targets mobile systems.

  • Many new power management features, both internally as well as on the FSB.

  • 400MHz, quad-pumped FSB.

  • 32-bit address bus.

  • Stack management implemented in hardware.

  • 1MB on-die L2 Cache. Banks are switched off when not in use.

Dothan06/04This is the second generation Pentium® M processor. As of this writing its introduction had slipped many times, but it was introduced in June of 2004. At its introduction, it had the following characteristics:

  • 400MHz, quad-pumped FSB.

  • 1.7 to 2.0GHz core speed.

  • Two flavors: low-voltage and ultra-low voltage.

  • Based on 90nm technology.

  • 2MB on die L2 Cache.

Celeron M Dothan01/06/04This model was released at 1.2 and 1.3GHz and had the following major features (in no particular order and not a complete list):

  • Based on the Dothan core.

  • 512KB on-die L2 Cache.

Merom20053rd generation Pentium® M processor (the successor to Dothan). Based on 90nm technology.
Gilo200665nm successor to Merom.

..................Content has been hidden....................

You can't read the all page of ebook, please click here login for view all page.
Reset
18.221.126.56