The Address and Data Strobes
Delivering the Request
When a transaction is initiated, the initiating agent outputs two packets of information that completely describe the transaction.
The P6 Request Delivery Method
Refer to Figure 43-2 on page 1120. On the P6 FSB, all of the other agents on the FSB latch the two packets on the rising-edge of the BCLK signal. The time it takes for the entire request (both packets) to be output is therefore two BCLK cycles.
Figure 43-2. Two Information Packets Broadcast during P6 Request Phase
The Pentium® 4/M Request Delivery Method
Refer to Figure 43-3 on page 1121. On the Pentium® 4/M FSB, two new Address Strobe signals, ADSTB[1:0]#, were added. The device that is initiating a transaction asserts ADS# (Address Strobe) to indicate that it is starting a new transaction. It also starts driving out packet A as well as ADSTB[1:0]#. It drives ADSTB[1:0]# low at the point where packet A should have arrived at the inputs of the receiving devices and stabilized. All agents on the FSB use the falling-edge of ADSTB[1:0]# to latch packet A. The initiator then drives out packet B and drives ADSTB[1:0]# high at the point where packet B should have arrived at the inputs of the receiving devices and stabilized. All agents on the FSB use the rising-edge of ADSTB[1:0]# to latch packet B. The Request Phase is said to be double-pumped.
Figure 43-3. Two Information Packets Broadcast during Pentium® 4/M Request Phase
The time it takes for the entire request to be output has been reduced to a single BCLK cycle.
Delivering the Data
When a transaction enters its Data Phase, between one byte and 64 bytes are transferred in (in eight-byte chunks; or, if eight bytes or less are being transferred, in a single chunk of between one and eight bytes).
The P6 Data Delivery Method
In Figure 43-4 on page 1123, a Memory Read transaction requesting a full cache line (32 bytes in the P6 processor family) enters its Data Phase in BCLK 9. In the example shown, the following actions take place:
A Snoop Agent indicates a hit on a modified line by asserting HITM# in BCLK 5.
The memory controller asserts TRDY# in clock 7 indicating it is ready to accept the modified line from the Snoop Agent.
As a result, the Snoop Agent takes ownership of the Data Bus in clock 9 by asserting the DBSY# (Data Bus Busy) signal.
The Snoop Agent drives the first qword onto D[63:0]# and asserts DRDY# (Data Ready) to indicate that valid data is present on the Data Bus.
The Request Agent (i.e., the device that initiated the transaction) and the memory controller latch the content of the Data Bus and the DRDY# signal on the rising-edge of BCLK 10. The valid state of DRDY# indicates that the first of the four qwords has been received.
On the rising-edge of BCLK 10, the Snoop Agent drives out the second qword and keeps DRDY# asserted to indicate valid data.
The Request Agent and the memory controller latch the content of the Data Bus and the DRDY# signal on the rising-edge of BCLK 11. The valid state of DRDY# indicates that the second of the four qwords has been received.
On the rising-edge of BCLK 11, the Snoop Agent drives out the third qword and keeps DRDY# asserted to indicate valid data.
The Request Agent and the memory controller latch the content of the Data Bus and the DRDY# signal on the rising-edge of BCLK 12. The valid state of DRDY# indicates that the third of the four qwords has been received.
On the rising-edge of BCLK 12, the Snoop Agent drives out the fourth qword and keeps DRDY# asserted to indicate valid data.
The Request Agent and the memory controller latch the content of the Data Bus and the DRDY# signal on the rising-edge of BCLK 13. The valid state of DRDY# indicates that the fourth and final qword has been received.
In the P6 FSB protocol, data is strobed into the receiving device's input receiver using the rising-edge of the BCLK, so the overall data transfer speed is limited by the BCLK frequency. It takes a minimum of four BCLK cycles to transfer 32 bytes.
The Pentium® 4/M Data Delivery Method
Refer to Figure 43-5 on page 1125. On the Pentium® 4/M FSB, eight new Data Strobe signals, DSTBP[3:0]# and DSTBN[3:0]#, were added and these high-speed strobes are used to transfer data from one device to another.
Figure 43-5. 64-Byte Transfer on the Pentium® 4/M FSB
The 64-bit Data Bus (D[63:0]#) is divided up into four groups of 16 data lines each (as well another signal line associated with each of the four groups):
Group 0 consists of D[15:0]# and the group 0 Data Bus Inversion signal, DBI0#.
Group 1 consists of D[31:16]# and the group 1 Data Bus Inversion signal, DBI1#.
Group 2 consists of D[47:32]# and the group 2 Data Bus Inversion signal, DBI2#.
Group 3 consists of D[63:48]# and the group 3 Data Bus Inversion signal, DBI3#.
One pair of Data Strobe signals is associated with each signal group:
DSTBP0# and DSTBN0# (a Positive strobe and a Negative strobe) are associated with group 0:
- The two falling-edges of DSTBP0# are used to latch words (a word is 16 bits) 1 and 3 from D[15:0]# and group 0's Data Bus Inversion signal into the receiving device's input receiver.
- The two falling-edges of DSTBN0# are used to latch words 2 and 4 from D[15:0]# and group 0's Data Bus Inversion signal into the receiving device's input receiver.
DSTBP1# and DSTBN1# (a Positive strobe and a Negative strobe) are associated with group 1:
- The two falling-edges of DSTBP1# are used to latch words 1 and 3 from D[31:16]# and group 1's Data Bus Inversion signal into the receiving device's input receiver.
- The two falling-edges of DSTBN1# are used to latch words 2 and 4 from D[31:16]# and group 1's Data Bus Inversion signal into the receiving device's input receiver.
DSTBP2# and DSTBN2# (a Positive strobe and a Negative strobe) are associated with group 2:
- The two falling-edges of DSTBP2# are used to latch words 1 and 3 from D[47:32]# and group 2's Data Bus Inversion signal into the receiving device's input receiver.
- The two falling-edges of DSTBN2# are used to latch words 2 and 4 from D[47:32]# and group 2's Data Bus Inversion signal into the receiving device's input receiver.
DSTBP3# and DSTBN3# (a Positive strobe and a Negative strobe) are associated with group 3:
- The two falling-edges of DSTBP3# are used to latch words 1 and 3 from D[63:48]# and group 3's Data Bus Inversion signal into the receiving device's input receiver.
- The two falling-edges of DSTBN3# are used to latch words 2 and 4 from D[63:48]# and group 3's Data Bus Inversion signal into the receiving device's input receiver.
Why Multiple Strobes?
As indicated in the previous section, both edges of a single signal DSTB# are not used to strobe the data into the input receivers. Rather, the falling edges of the DSTBP# and DSTBN# signals are used.
There is very minimal jitter in the period between two, consecutive falling edges (or rising edges) of a strobe, but there can be significant jitter in the period between rising and falling edge of that strobe. In order to keep the sample periods constant with no jitter, it is therefore better to use the falling edges of two different strobes that are out of phase by 180 degrees rather than using the rising and falling edge of one strobe which can jitter significantly.
The second reason is that a single strobe signal usually does not have a duty cycle of 50%/50%. Rather, strobe signals (like clocks) tend to have duty cycles of 60%/40%. This is due to the fact that the 'p' and 'n' transistors in the p-n transistor strobe driver circuits have different drive strengths resulting in signals that do not have 50%/50% duty cycle characteristic. þUsing the rising and falling edges of the same signal to sample results in sample windows with different periods.
The Data Bus Inversion Signals
The more signal lines that an agent must simultaneously assert (i.e., drive low), the more power it takes. The Pentium® 4/M FSB protocol uses a clever little method to decrease the power consumed while data is being transferred over the Data Bus (as an added benefit, ground-bounce is also reduced).
As mentioned earlier, the Data Bus (D[63:0]#) is divided into four 16-bit groups of signal lines and each group has a Data Bus Inversion (DBIn#, where n = the Data Bus group number) signal associated with it. Before an agent drives data each signal group, it pre-evaluates the 16 bits of data to be driven. If more than eight (more than half) would have to be driven low, the device inverts the 16-bit data pattern before driving it onto the bus. When the device receives the 16-bits of data, it checks the state of the signal group's DBI signal and if it's asserted, the data was inverted before being driven. If this is the case, the receiving device knows that the data was inverted.
Address and Data Strobe Setup and Hold Specs
The following are the timing specifications for ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]# and the input receiver setup and hold specs:
The input receiver Setup Time is a minimum of 0.21ns.
The input receiver Hold Time is a minimum of 0.21ns.
The interval from the arrival of a signal at the input receiver to the next rising-edge of BCLK0 at VCROSS is a minimum of 0.65ns.
The interval from the falling-edge of an Address Strobe signal to the rising-edge of the same Address Strobe signal is a maximum 1/2 of a BCLK cycle.
Refer to Figure 43-5 on page 1125. Regarding the timing within a Data Strobe signal pair, four chunks of data are transferred using the strobe edges in the following order:
- The first data chunk is transferred on the first falling-edge of the positive strobe signal in the pair.
- The second chunk is transferred on the first falling-edge of the negative strobe signal in the pair. This transfer must occur approximately 1/4 of a BCLK period after the first transfer.
- The third data chunk is transferred on the second falling-edge of the positive strobe signal in the pair. This transfer must occur approximately 1/2 of a BCLK period after the second transfer.
- The fourth chunk is transferred on the second falling-edge of the negative strobe signal in the pair. This transfer must occur approximately 3/4 of a BCLK period after the first transfer.