PSE-36 Mode
PSE-36 Mode Background
Only one new software feature was introduced in the Pentium® II Xeon processor. This is the PSE-36 feature and it is described in the sections that follow.
Prior to the introduction of PAE-36 Mode (see “PAE-36 Mode” on page 554) in the Pentium® Pro processor, IA32 processors could only address up to 4GB of physical memory (refer to Figure 29-3 on page 732). Using a 3-level directory lookup (rather than the 2-level, 386-compatible Paging mechanism), PAE-36 Mode permitted the OS to map a 32-bit linear memory address to any address within the processor's 64GB physical memory address space. However, implementing PAE-36 Mode necessitated a rewrite of the paging portion of the OS kernel to use the 3-level directory structure. In addition, entries in each of the three directory structures (i.e., the PDPT, the Page Directories, and the Page Tables) had to be expanded from 32-bits to 64-bits in width.
In addition to PAE-36 Mode, the Pentium® II Xeon processor implemented an alternative feature referred to as PSE-36 Mode. It did not require a major rewrite of the paging portion of the OS kernel. It uses the same 2-level directory structure as does the 386-compatible paging mechanism and each entry in the Page Directory and the Page Tables is still 32 bits in width. However, as will be described in the sections that follow, PSE-36 Mode is neither as elegant as, nor as flexible as PAE-36 Mode.
Intel® collectively refers to the PSE-36 and PAE-36 features as ESMA (Extended Server Memory Architecture).
Detecting PSE-36 Mode Capability
The programmer can determine whether or not a processor supports PSE-36 Mode by executing a CPUID request type 1 and checking EDX[17] to see if it is set to one. It should be noted that Intel® documentation (specifically on page - of IA32 Intel® Architecture Software Developer's Manual Volume 2: Instruction Set Reference) incorrectly refers to EDX bits 3 and 17 as the PSE bit. While EDX[3] is the PSE (Page Size Extension; see “4MB Pages” on page 501) feature bit, EDX[17] is the PSE-36 feature bit.
Enabling PSE-36 Mode
Assuming that a processor supports PSE-36 Mode (see the previous section), the OS can enabled it by turning off PAE-36 Mode and turning on PSE Mode (i.e., 4MB Page capability). In other words, it is enabled by clearing CR4[PAE] to zero and setting CR4[PSE] = 1 (see Figure 29-4 on page 733). Turning on PSE Mode simultaneously enables 4MB page capability and PSE-36 Mode.
Per Application Linear Memory Space = 4GB
Turning on PAE-36 or PSE-36 Mode does not change the fact that the currently executing program can only specify 32-bit linear memory addresses for memory accesses that it must perform. In other words, the program is still limited to a 4GB linear memory address space. However, a 32-bit linear address can be translated into a 36-bit physical memory address that is either below or above the 4GB address boundary.
386-Compatible Directory Lookup Mechanism
The 386-compatible Paging mechanism was described in “386 Demand Mode Paging” on page 209. It utilizes a 2-level directory lookup (refer to Figure 29-5 on page 734) to convert a 32-bit linear memory address into a 32-bit physical memory address (limiting it to translating a linear address into a physical memory address within the lower 4GB of physical memory address space).
Figure 29-5. 386-Compatible, 2-Level Lookup Mechanism
Selected PDE Can Point to 4KB Page Table or a 4MB Page
As mentioned earlier, PSE-36 mode uses the 2-level address translation mechanism used by the 386-compatible Paging mechanism. The upper 10 bits of the 32-bit linear address is used as an index into the Page Directory, selecting a 32-bit PDE. With PSE-36 Mode enabled, however, the PDE can have either of two possible formats:
The PDE may point to a Page Table that defines the location of the 1024, 4KB pages that comprise the page group selected by the upper 10-bits of the linear address. In other words, the lookup converts the 32-bit linear address into a 32-bit physical address in the lower 4GB of physical memory space. This is traditional 386-compatible Paging (see “386 Demand Mode Paging” on page 209 for a complete description).
The PDE may contain the base address of a 4MB page that lies either below or above the 4GB address boundary. See the next section.
Linear Address Maps to a 4MB Page in 64GB Space
If the PDE[PS] = 1 in the selected PDE, then the PDE has the format illustrated in Figure 29-6 on page 736. Taken together, the two bit fields labelled PA-1 and PA-2 (Physical Address fields) define the upper 14 bits of the 36-bit, 4MB-aligned base address of a 4MB physical page in memory. The Paging Unit appends the lower 22 bits of the linear address to the 14 bits from the PDE to create the 36-bit target physical memory address.
Figure 29-6. PDE Points to a 4MB Page Below or Above the 4GB Address Boundary
Of course, if the PDE[P] bit = 0, the processor experiences a Page Fault exception (see “When the Target Page Table Isn't in Memory” on page 225). This can happen for one of two reasons:
The Page Table the entry should point to is currently not in memory.
The 4MB page of information is currently not in memory.
The OS Page Fault exception handler must make the determination which of these two conditions is the case and take the appropriate action (i.e., either load the 4KB Page Table or the 4MB page into memory).
Windows and PSE36
Microsoft Windows implemented PSE-36 Mode as a RAM disk driver. The following sequence illustrates how it works:
The application must be rewritten so as to call the driver when it needs to access memory above the 4GB address boundary.
The OS does not enable or use PSE-36 Mode.
When called, the driver temporarily turns on PSE-36 Mode to accomplish the access above the 4GB address boundary for the calling application.
As an example, to write to memory above the 4GB boundary, the following steps are taken:
1.The application writes the data to be transferred into a buffer somewhere in the lower 4GB of memory.2.The application then calls the PSE-36 Mode driver with a request to transfer the data from the buffer in memory below the 4GB address boundary into memory above the 4GB address boundary.3.The driver temporarily switches the processor into PSE-36 mode.4.The driver copies the data from the buffer in the lower 4GB of memory to a memory buffer above the 4GB boundary.5.The driver turns off PSE-36 mode and returns control to the caller.A read would require the reverse of the actions listed.
It should be obvious that performance is poor due to need for the buffer copy operation. It should also be stressed that all applications still share the lower 4GB of memory.