Chapter 36. Pentium^® 4 PowerOn Configuration

The Previous Chapter

This chapter provided an overview of the Pentium® 4 processor. This included:

• The Pentium® 4 Processor Family.

• Pentium® III/Pentium® 4 Differences.

• Pentium® 4/Pentium® 4 Prescott Differences.

• Pentium® 4 Processor Basic Organization.

• The FSB is Tuned for Multiprocessing.

• Intro to the FSB Enhancements.

• IA Instructions and μops.

• The Trace Cache.

• The μop Pipeline.

• The Alias Registers.

• Speculative Execution.

This Chapter

This chapter provides a detailed description of the automatic configuration of the Pentium® 4 processor when the system is first powered up. This includes:

• Setup and Hold Time Requirements.

• Built-In Self-Test (BIST) Trigger.

• The Cluster ID Assignment.

• The Agent ID Assignment.

• The Local APIC ID Assignment.

• Error Observation Options.

• In-Order Queue Depth Selection.

• Power-On Restart Address.

• Tri-State Mode.

• Processor Core Speed Selection.

• Bus Parking Option.

• Hyper-Threading Option.

• Program-Accessible Startup Features.

The Next Chapter

This chapter provides a detailed description of the processor's state immediately after reset is removed. It also describes how the Boot Strap Processor (BSP) is selected, as well as the Application Processor discovery and configuration process. This discussion includes:

• The Processor's State After Reset.

• EAX, EDX Content After Reset Removal.

• The Core Is Starving and Caching is Disabled.

• Boot Strap Processor (BSP) Selection.

• How the APs are Discovered and Configured.