Data Prefetch Instruction Execution Enhanced

The software data PREFETCHh instructions were introduced in the Pentium® III processor and were described in “Overlapping Data Prefetch with Program Execution” on page 773.

On all Pentium® 4 processors, the software PREFETCHh instructions read prefetch data into the L2 Cache on a cache miss. In the earlier versions of the Pentium® 4 processor, a PREFETCHh instruction was silently dropped if it resulted in a DTLB miss.

In the event of a DTLB miss, the 90nm version of the Pentium® 4 processor performs a lookup in the Page Directory and a Page Table and, if the target PTE or PDE is valid, it is read into the DTLB and is used to perform a lookup in the cache for the PREFETCHh instruction. If the target PTE or PDE is not valid, a Page Fault exception is not generated. Rather, the PREFETCHh instruction is just silently dropped.

As pointed out in “Enhanced Trace Cache μop Encoding” on page 1093, as an added bonus the software PREFETCHh instructions are now cached in the Trace Cache and do not have go to the MS ROM for decode.