Everything's Relative
All AGTL+ Signals Are Active When Low
All AGTL+ signal names (e.g., A5#, D63#, BR0#) are followed by the # symbol, indicating that they are in the asserted state when driven low. As a result of this, before the address and data are driven onto the address and data signal lines, they are inverted:
An address or data bit that is internally represented by an electrical one is inverted to an electrical zero when it is driven onto its respective address or data signal line.
An address or data bit that is internally represented by an electrical zero is inverted to an electrical one when it is driven onto its respective address or data signal line.
Note that data bus inversion may cause some of the 16-bit data groups to be inverted yet again (see “The Data Bus Inversion Signals” on page 1125).
All AGTL+ Signals Are Terminated
All AGTL+ signal lines are terminated on either end of the trace with a pull-up resistor (RTT).
On the earlier P6 processors (i.e., the Pentium® Pro and the Pentium® II), these termination resistors were on the system board.
On the cartridge-based Pentium® III processors, the termination resistors were on the cartridge.
On the Pentium® 4 processor, the termination resistors for many of the AGTL+ signals are on the processor die (see Table 43-3 on page 1128 and Table 43-4 on page 1129). Some versions of the processor implement an input signal (ODTEN; On-Die Termination Enable) that can be used to activate or deactivate the processor's on-die termination resistors. It should be connected to VCC to enable on-die termination for end bus agents. For middle bus agents, pull this signal down via a resistor to ground to disable on-die termination. Whenever ODTEN is high, on-die termination will be active, regardless of other states of the bus.
Table 43-3. Prescott AGTL+ Signals with On-Die Termination Signal(s) Description A[35:3]# The qword-aligned Address Bus. ADS# Address Strobe. ADSTB[1:0]# The double-pumped Address Strobes. AP[1:0]# The Address Bus parity bits. BINIT# The Bus Initialization signal. BNR# The Block Next Request signal. BOOTSELECT The author finds the name of this pin intriguing, but the following is the only description that Intel® documentation offers: “This input is required to determine whether the processor is installed in a platform that supports the processor. The processor will not operate if this pin is low. This input has a weak internal pull-up.”
BPRI# The Bus Priority Agent Request signal. D[63:0]# The 64-bit Data Bus. DBI[3:0]# The four Data Bus Inversion signals. DBSY# The Data Bus Busy signal. DEFER# The Defer or Retry signal. DP[3:0]# The Data Bus Parity bits. DRDY# The Data Ready signal. DSTBN[3:0]# and DSTBP[3:0]# The quad-pumped data strobes. HIT# and HITM# The Snoop Result signals. LOCK# The Lock Signal. MCERR# The Machine Check Error signal. OPTIMIZED/COMPAT# The author finds the name of this pin intriguing, but the following is the only description that Intel® documentation offers: “This signal should be left as a no connect on the baseboard to indicate that the baseboard supports the 90nm Pentium® 4 processor. This input has a weak internal pull-up.”
PROCHOT# The Processor Hot signal. REQ[4:0]# The Request Bus. RS[2:0]# The Response Bus. RSP# The Response Bus parity bit. TRDY# The Target Ready signal. Table 43-4. Prescott AGTL+ Signals without On-Die Termination Signal(s) Description A20M# The Address bit 20 Mask input. BPM[5:0]# The Breakpoint/Performance Monitoring counter outputs. BR0# The Bus Request 0 signal. FERR#/PBE# The FP Error or Pending Break Event output. IERR# The Internal Error output. IGNNE# The Ignore Numeric Error Input. INIT# The Soft Reset input. LINT0/INTR Local Interrupt pin 0/Interrupt Request input. LINT1/NMI Local Interrupt pin 1/Non-Maskable Interrupt input. RESET# The Hard Reset input. SKTOCC# The Socket Occupied output. SLP# The Sleep input. SMI# The System Management Interrupt input. STPCLK# The Stop Clock input. THERMTRIP# The Thermal Trip output. GTLREF[3:0] The AGTL+ Reference voltage inputs.
On the pre-90nm Pentium® 4 processors, the termination voltage (VTT) was equal to the processor die's operating voltage, VCC. The processor does not have on-die termination resistors for the signals shown in Table 43-4 on page 1129, so they require termination resistors on the system board.
On the 90nm Pentium® 4 processor, the termination voltage (VTT) is:
- Minimum = 1.35VDC.
- Nominal = 1.45VDC.
- Maximum = 1.55VDC.
Deasserting an AGTL+ Signal Line
On the early P6 processors, the FSB signals were referred to as GTL+ rather AGTL+ signals. The protocol for deasserting a signal (i.e., for returning it to the electrically-high state after asserting it) was simply to stop driving it low. The termination resistors were responsible for returning the signal to the deasserted (i.e., electrically-high) state. The problem with this approach is obvious: the pull-up resistor was slow to return a signal to the electrical high state and the signal line would ring for a while before settling down to the high state.
Starting with the later versions of the P6 processor family and continuing with the Pentium® 4 and Pentium® M processor families, the protocol for returning a signal line to the deasserted state requires the device that was driving the signal low to actively drive it high for one BCLK cycle and then back its output driver off of the signal line. The spec name was changed from GTL+ to AGTL+ (Assisted GTL+) at that time.
Each AGTL+ Input Has a Comparator
Refer to Figure 43-6 on page 1132.
Figure 43-6. AGTL+ Input Receiver
The Reference Voltage
A device determines the state of an AGTL+ input by sampling the voltage level on the input and comparing it to a reference voltage supplied to the device on its GTLREF inputs by a voltage divider on the system board.
On the pre-90n versions of the Pentium® 4 processor, the reference voltage was two-thirds (2/3) of VTT (the termination voltage) and the termination voltage was equal to the processor die's operating voltage, VCC.
On the 90nm version of the Pentium® 4 processor, the reference voltage is 0.63 multiplied by the processor die's operating voltage, VCC.
The Sample Point
An AGTL+ signal is sampled when the rising-edge of BCLK0 crosses Vcross (Vcross is when the voltage level on BCLK0 and BCLK1 are equal). The voltage sampled is then compared to the AGTL+ Reference Voltage to determine if it's an electrical high or low. The comparison is described in the two sections that follow.
The Pre-90nm Comparison
Refer to Figure 43-6 on page 1132. The sampled voltage level is compared to the GTLREF voltage (2/3 of VCC±2%):
Refer to Figure 43-7 on page 1133. Any value from 10% above the GTLREF voltage up to VCC is considered to be an electrical high. In other words, the signal is deasserted and a logical zero will therefore be supplied to the core.
Refer to Figure 43-8 on page 1134. Any value from 0.0VDC to 10% less than GTLREF is considered to be an electrical low. In other words, the signal is asserted and a logical one will therefore be supplied to the core.
The 90nm Comparison
Refer to Figure 43-6 on page 1132. The sampled voltage level is compared to the GTLREF voltage (63% of VCC ±2%):
Refer to Figure 43-7 on page 1133. Any value from 10% above the GTLREF voltage up to VCC is considered to be an electrical high. In other words, the signal is deasserted and logical zero will therefore be supplied to the core.
Refer to Figure 43-8 on page 1134. Any value from 0.0VDC to 10% less than GTLREF is considered to be an electrical low. In other words, the signal is asserted and logical one will therefore be supplied to the core.
AGTL+ Setup and Hold Specs
The setup and hold times for all of the common clock AGTL+ signals are as follows:
Setup spec: A signal must have arrived at its final value at the latest by 0.65ns prior to the sample point.
Hold spec: A signal must remain stable until at least 0.40ns after the sample point.