The Deep Sleep State

Refer to Figure 27-6 on page 694. This is the lowest power conservation state that the processor can be in and still maintain the contents of its registers and caches. The Deep Sleep state has the following characteristics:

• It can only be entered after the processor has entered the Sleep state.

• The processor enters the Deep Sleep state immediately when the system board logic stops the BCLK input to the processor's PLL. Intel® recommends that the BCLK be stopped in the low state, lowering current consumption to leakage levels.

• To exit the Deep Sleep state and return to the Sleep state, the BCLK must be restarted and continue to run for a period of at least 1ms.

• Snoop events that occur on the FSB while the processor is in the Deep Sleep state will result in unpredictable behavior.

• No transitions or assertions of signals are allowed on the FSB while the processor is in the Deep Sleep state. Any transitions on any input signal before the processor has returned to the Stop Grant state will result in unpredictable behavior.

Figure 27-6. The Deep Sleep State

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