Uniprocessor vs. Multiprocessor Bus

The FSB utilized on IA32 processors prior to the advent of the P6 processor family was ill-suited in a platform wherein multiple processors reside on the FSB (see Figure 44-1 on page 1140).

The Pentium® Pro FSB was specifically designed to support multiple processors on the same bus, and the Pentium® 4/M FSB is a derivative of the P6 FSB. The following major changes were made:

• In a typical Pentium® 4/M FSB environment, up to 12 transactions can simultaneously be in progress at various stages of completion.

• If the target of a transaction (i.e., the Response Agent) cannot deal with a new transaction right now (e.g., due to a temporary logic busy condition), rather than tie up the bus by inserting wait states, it will issue a Retry response to the initiator. This causes the Request Agent to rearbitrate for ownership of the FSB and retry the transaction again at a later time. This frees up the FSB for other initiators.

• If the target of a read or write transaction determines that it will take a fairly long time to complete the data transfer (i.e., to provide read data or to accept write data), it can issue a Deferred response to the Request Agent. This instructs the Request Agent to terminate the transaction without transferring any data. When the Response Agent has obtained the requested read data or has delivered the write data, it arbitrates for ownership of the FSB and initiates a Deferred Reply transaction to complete the transfer. This is referred to as transaction deferral.

These mechanisms prevent any properly-designed FSB agent from tying up the FSB for extended periods of time. A detailed description of the processor's FSB is presented in the subsequent chapters of the book.