The MFENCE Instruction

The Memory Fence instruction (first implemented in the Pentium® 4 processor) acts as a fence that prevents the processor from executing any loads or stores beneath the fence until all loads and stores above the fence have been completed and the processor's Store Buffers and WCBs have been drained to memory:

mov  eax,10
mov  ebx,memioport1  ;read from memory mapped IO port 1
mov  edx,memioport2  ;read from memory mapped IO port 2
mov  memioport3,eax  ;write to memory mapped IO port 3
xor  eax,edx
mfence               ;cannot perform loads/stores beyond
                     ;fence until all prior loads have
                     ;completed
mov  ecx,memioport4  ;read from memory mapped IO port 4

While the processor cannot execute loads or stores beneath the fence until all upstream loads and stores have been completed and the processor's Store Buffers and WCBs have been drained to memory, the processor can execute non-memory μops beneath the fence before all of the loads, stores and buffer draining above the fence have been completed. In the following example, the programmer has used the CPUID instruction to accomplish the same goal:

mov  eax,10
mov  ebx,memioport1  ;read from memory mapped IO port 1
mov  edx,memioport2  ;read from memory mapped IO port 2
mov  memioport3,eax  ;write to memory mapped IO port 3
xor  eax,edx
mov  eax,1           ;set up for a CPUID request type 1
cpuid                ;acts as a barrier in the code
mov  ecx,memioport4  ;read from memory mapped IO port 4

CPUID is a serializing instruction (see “Serializing Instructions” on page 1079). The processor cannot execute any μop beneath the fence until all of the μops above the fence have been executed and retired. This causes a significant drop in performance due to the constraint placed on out-of-order execution. Using the MFENCE instruction results in better performance.

Although the example assumed that the memory locations read were in UC memory space, the MFENCE instruction can be used to fence loads and stores from any type of memory space.

Using the LFENCE and SFENCE instructions is not equivalent to using the MFENCE instruction. The load and store fences are not ordered with respect to each other: the LFENCE can be executed before prior stores, and the SFENCE can be executed before prior loads. The MFENCE instruction should be used whenever the Cache Line Flush instruction (CLFLUSH) is used to ensure that speculative memory references generated by the processor do not interfere with the flush.