The Machine Check Architecture
Introduction
With the advent of the Pentium® 4 processor, the Machine Check Architecture (MCA) became part of the IA32 processor architecture spec. It is therefore guaranteed to operate in the same manner in future IA32 processors. In addition, with the exception of the items described in this section, it is backward compatible with the MCA implementations on the Pentium® and P6 processor families [see “MCA Enhanced” on page 588 and “Machine Check Architecture (MCA)” on page 504].
The MCA is the processor's internal error logging facility. It logs both soft (i.e., correctable) errors as well as hard errors. If the processor is enabled to generate the Machine Check exception (CR4[MCE] = 1), the exception is generated whenever a hard error is logged. For a complete description of the MCA, refer to “MCA Enhanced” on page 588.
The Pentium® 4 MCA Enhancements
The IA32_MCG_CAP MSR (Global CAP = Count and Present) is implemented differently in the Pentium® 4 than in the P6 processors. It is a read-only register that provides information about the MCA implementation and contains the following (see Figure 56-16 on page 1364):
Count field. Indicates the number of error logging register banks that are implemented in a processor. While the P6 processors had five banks of MCA registers, the Pentium® 4 has four (see Figure 56-17 on page 1364).
MCG_CTL_P (MC Global Control register Present). 1 indicates that the processor implements the IA32_MCG_CTL MSR.
MCG_EXT_P (MC Extended registers Present). 1 indicates that the processor implements the extended MCA state registers (see “The Extended MC State MSRs” on page 1364).
MCG_EXT_CNT field. Indicates the number of extended MCA state registers that are present (meaningful only when MCG_EXT_P = 1). The Pentium® 4 processors implement 10 of them. See “The Extended MC State MSRs” on page 1364.
The Extended MC State MSRs
These registers were added with the advent of the Pentium® 4 processor. When a Machine Check exception is generated, the processor automatically snapshots the GPRs, EIP, and EFlags in these registers (see Table 56-3 on page 1365) to be used by the Machine Check exception handler.
| Register | is copied into this MC State Save MSR |
|---|---|
| EAX | IA32_MCG_EAX |
| EBX | IA32_MCG_EBX |
| ECX | IA32_MCG_ECX |
| EDX | IA32_MCG_EDX |
| ESI | IA32_MCG_ESI |
| EDI | IA32_MCG_EDI |
| EBP | IA32_MCG_EBP |
| ESP | IA32_MCG_ESP |
| EFlags | IA32_MCG_EFLAGS |
| EIP | IA32_MCG_EIP |
| The state save MSR registers shown above occupy sequential MSRs addresses and are immediately followed by the IA32_MCG_MISC register. This 64-bit register currently contains just one unreserved bit, bit 0. It is the DS status bit and when set to one, it indicates that a Page Assist or Page Fault occurred while the Debug Store mechanism was attempting to store either a Branch Trace record or a PEBS record in the DS save area in memory [see “The Debug Store (DS) Mechanism” on page 1366 for more information]. The processor enters the Shutdown state. This bit is set as an aid for debugging the DS handling code. Software must clear this bit to return the processor to normal DS operation. | |
| The series of 32 MSR addresses immediately following that of the IA32_MCG_MISC register are reserved for the addition of up to 32 additional state save registers in future implementations. | |