The Signals

Table 55-1 on page 1314 provides a description of each of the processor pins that were not covered in the chapters on the Pentium® 4 FSB protocol.

Table 55-1. Miscellaneous Signals
Signal(s)Description
A20M#Address bit 20 Mask. Input. See “A20 Mask” on page 419.
BINIT#

Bus Initialization. Input/output. BINIT# is asserted by an agent when the FSB cannot be reliably used for future transactions. As an example, if an agent's IOQ is corrupted, it can no longer reliably track transactions and therefore cannot reliably interact with the FSB at the appropriate times. How a processor uses BINIT# is set up as follows:

When BINIT# is detected, all agents clear their IOQs, their Deferred Transactions Queues, and also reset their FSB interface state machines to the Idle ownership state and a Rotating ID to 3.

The processor can be enabled to generate a Machine Check exception when BINIT# is detected or asserted. The MCA registers can log an error indicating that either the processor observed someone else assert BINIT# or that it asserted BINIT#. The Intel® documentation doesn't say, however, which processor will execute its Machine Check exception handler. The author assumes it would be the processor that asserted BINIT#. Multiple processors could observe it asserted by another agent and you wouldn't want all of them simultaneously executing the Machine Check exception handler.

There is the possibility that an agent other than a processor asserted BINIT#. In this event, the central agent (e.g., the Root Complex), could be configured to send an NMI message to the processors as an interrupt message over the FSB. BINIT# is one of the FSB signals that may be driven by multiple agents simultaneously (i.e., it is an open-drain signal). The protocol demands that when BINIT# is asserted, it remain asserted for exactly three clocks.

  • If an agent samples BINIT# deasserted in the clock that the agent asserts it, it asserts BINIT# for exactly three clocks and then releases it.

  • If BINIT# was already asserted by one or more other agents prior to an agent's assertion of BINIT#, it must only assert BINIT# for two clocks or one clock, depending on how long it has already been observed asserted. This results in BINIT# only being asserted for exactly three clocks.

BOOTSELECTInput. This input was introduced on the 90nm version of the Pentium® 4 processor. Its state determines whether the processor is installed in a platform that supports it. The processor will not operate if this pin is low. This input has a weak internal pull-up.
BPM[3:0]#Outputs. Breakpoint or Performance Monitor Counter output pins. There's something of a mystery here. On the P6 processor family, bits in the DebugCtl MSR were used to select whether these pins would be used to indicate one of the following:

  • When one of the four debug breakpoints had a match, or

  • When one of the Performance Monitor Counters experienced an overflow.

Intel® public-domain documentation for the Pentium® 4 processor, however, makes no reference whatsoever to how the programmer chooses which of the these two event types are signalled on these output pins.

Starting with the 386, all IA32 processors incorporates a set of Debug registers that can be used to set up and enable up to four program breakpoints (breakpoints 0 through 3). If an internal access matches the breakpoint conditions defined for one of these breakpoints, the processor asserts the respective output.

The Pentium® 4 processor implements 18 Performance Monitoring Counters.
PM[5:4]#Outputs. The processor can be programmed to assert these pins when a Performance Monitoring Counter overflows.

  • BPM4# also acts as the PRDY# (Probe Ready) signal to the TAP (Test Access Port) boundary scan port. PRDY# is asserted by the processor in response to a debug tool's assertion of PREQ# and indicates that the processor has entered Probe Mode.

  • BPM5# also acts as the PREQ# (Probe Request) signal from the TAP port boundary scan port. A debug tool asserts PREQ# to request that the processor enter Probe Mode so the tool can inject commands and requests into the processor via the boundary scan interface.

Refer to “Test Access Port (TAP)” on page 481 for additional information about the TAP.
BSEL[1:0]Outputs. See “Processor Core Speed Selection” on page 867.
COMP[1:0]COMP[1:0] must be terminated to VSS (ground) on the system board using precision resistors (60 fl ± 15%). These inputs configure the AGTL+ drivers of the processor.
DBR#Output. DBR# (Data Bus Reset). It is used only in systems where no debug port is implemented on the system board. DBR# is used by a debug port interposer so that an In-Target Probe (ITP) can drive system reset. If a debug port is implemented in the system, DBR# is a no-connect in the system. DBR# is not a processor signal.
FERR# output or PBE# inputThe purpose of this pin is defined by the state of bit 10 in the IA32_MISC_ENABLE MSR (see Figure 56-21 on page 1373):

  • When bit 10 = 1:

    - (and the processor's STPCLK# input has not been asserted by the chipset). An x87 FP error results in the assertion of the processor's FERR# output (assuming that CR0[NE] = 1; see “FP Error Reporting” on page 444).

    - If the chipset had asserted STPCLK# to the processor to place the processor in a low-power state (see “The Stop Grant State” on page 688) and the chipset then has an interrupt that requires servicing, the chipset asserts the processor's PBE# (Pending Break Event) input. This causes the processor to return to the Normal state to service the interrupt.

  • When bit 10 = 0, the processor's ability to report an x87 FP error by asserting its FERR# output is disabled.

A processor's support for the PBE# capability is determined by executing a CPUID request type 1 and checking for a one in EDX[31] (see Figure 56-6 on page 1333).
GTLREFInput. The voltage provided on the processor's GTL Reference input is the reference voltage used by the AGTL+ input receiver comparators. See “Everything's Relative” on page 1127.
IERR#Output. Internal Error is generated by a processor when an unrecoverable internal error is detected that is not handled by the MCA logic (because it is disabled). The processor can also be configured to assert BINIT## once along with IERR# (see Figure 36-11 on page 873).
IGNNE#Input. Ignore Numeric Error. Refer to “FP Error Reporting” on page 444.
INIT#Input. Soft Reset. Refer to “Soft Reset (INIT#)” on page 485.
ITP_CLK[1:0]Inputs. In-Target Probe tool clock. Implemented on the 130nm and the 90nm Pentium® 4, but not on the Pentium® 4 Xeon processor. This is a copy of BCLK and is used only in systems without a debug port on the system board. They are used as BCLK[1:0] references for a debug port implemented on an interposer. If a debug port is implemented, they are no-connects. These are not processor signals.
ITPCLKOUT[1:0]Outputs. Implemented on the 130nm Pentium® 4, but not on the Pentium® 4 Xeon or on the 90nm Pentium® 4. ITPCLKOUT[1:0] is an uncompensated differential clock output and is a delayed copy of BCLK[1:0]. It can be used as the differential clock for an ITP port on the system board. If they are not used, they must be terminated properly.
MCERR#Input/Output. Machine Check Error is asserted to indicate that an unrecoverable error was detected either within the processor or external to the processor. It may be driven by any FSB agent. The processor's ability to observe MCERR# as an input and its ability to assert MCERR# can be configured (see “Program-Accessible Startup Features” on page 869 and Figure 36-11 on page 873). This is an open-drain signal that may be driven by multiple agents simultaneously. The protocol demands that when MCERR# is asserted, it remain asserted for exactly three clocks.

  • If an agent samples MCERR# deasserted in the clock that the agent asserts it, it asserts MCERR# for exactly three clocks and then releases it.

  • If MCERR# was already asserted by one or more other agents prior to an agent's assertion of MCERR#, it must only assert MCERR# for two clocks or one clock, depending on how long it has already been observed asserted. This results in MCERR# only being asserted for exactly three clocks.

ODTENInput. On-die Termination Enable. Should be connected to Vcc to enable on-die termination for agents residing at the physical ends of the FSB. For middle FSB agents, pull this signal down via a resistor to ground to disable on-die termination. Whenever ODTEN is high, on-die termination will be active.
OPTIMIZED/COMPAT#Input. Must be a no-connect on a system board that supports the 90nm Pentium® 4 processor. This input has a weak internal pull-up.
PROCHOT#Input/Output. Processor Hot:

  • Output. Asserted when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature. This indicates that the processor Thermal Control Circuit (TCC) has been activated, if enabled (see “The Thermal Monitoring Facilities” on page 1340 for more information).

  • As an input, assertion of PROCHOT# by the chipset activates the TCC, if enabled. The TCC remains active until the chipset de-asserts PROCHOT#.

PWRGOODInput. Power Good. When asserted, it indicates that the clocks and power supply voltages are stable and within their spec. The signal remains deasserted (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they arrive at the spec levels. It must then transition monotonically to the asserted state. It can be deasserted at any time (due to a degradation of the clocks or supply voltages), but it must not be reasserted until the clocks and supply voltages are once again within spec. It must remain asserted while boundary scan operations are in progress.
RESET#Input. Hard Reset. When asserted to the processor, the processor is set to the initialized state (see “Pentium® 4 Processor Startup” on page 875) and all of its caches are invalidated (modified lines are not written back to memory). At power-on time, RESET# must stay asserted for at least 1ms after VCC and BCLK are within spec. All FSB agents (including the processor) must deassert their outputs within two BCLK cycles. RESET# must not remain asserted for more than 10ms. On the trailing-edge of RESET#, the processor samples a number of its FSB signals to configure some of its operational characteristics (see “Pentium® 4 PowerOn Configuration” on page 855). RESET# does not have on-die termination and must be terminated at the end agent.
SKTOCC#Output. Socket Occupied is asserted (grounded) by the processor when it is installed. The chipset may use this pin to determine if the processor is present.
SLP#Input. If the chipset asserts the processor's Sleep input while the processor is in the Stop Grant state (see“The Stop Grant State” on page 688), the processor enters the Sleep state (see “The Sleep State” on page 692). When SLP# is deasserted, the processor exits the Sleep state and returns to Stop Grant state.
SMB_PRTThese signals are related to the Pentium® 4 Xeon processor's SMBus interface. See “SMBus (System Management Bus)” on page 723 for additional information.
SM_ALERT#
SM_CLK
SM_DAT
SM_EP_A[2:0]
SM_TS_A[1:0]
SM_VCC
SM_WP
STPCLK#Input. When the chipset asserts Stop Clock to the processor, the processor enters the Stop Grant state (see “The Stop Grant State” on page 688). When STPCLK# is deasserted, the processor exits the Stop Grant state and re-enters the fully-operational Normal state (see “The Normal State” on page 686).
TCK, TDI, TDO, TMS, TRST#Test Clock, Test Data In, Test Data Out, Test Mode Select and Test Reset all comprise the processor's boundary scan interface. A discussion of boundary scan is outside the scope of this book.
TESTHI[x:0]Inputs. The number of TESTHI inputs implemented is processor design-specific. All TESTHI pins must be individually connected to VCC via a pull-up resistor that matches the trace impedance within a range of ± 10fl. Boundary scan testing will not be functional if these pins are connected together. For optimum noise margin, all pull-up resistor values used must have a resistance value within ± 20% of the impedance of the system board transmission line traces. For example, if the trace impedance is 50 fl, then a value between 40fl and 60fl must be used.
THERMDA, THERMDCThese are the processor's Thermal Diode Anode and Cathode pins. The processor incorporates an on-die thermal diode. In addition, a thermal sensor on the system board (connected to these two pins) may monitor the die temperature of the processor for thermal management. While they are implemented on the 130nm and 90nm Pentium® 4 processors, they are not implemented on the Pentium® 4 Xeon processor.
THERMTRIP#Output. Thermal Trip. The processor automatically shuts down when the silicon has reached a temperature approximately 20 °C above the maximum TC. The assertion of the processor's Thermal Trip output indicates that the processor's junction temperature has reached a level beyond which permanent silicon damage may occur. The processor turns off its internal clocks to reduce the junction temperature. To protect the processor, the chipset must command the system board voltage regulator to turn off the processor die's core voltage (VCC) supply when it detects THERMTRIP# asserted. The processor's ability to assert THERMTRIP# is enabled within 10μs of the assertion of PWRGOOD and is disabled on the deassertion of PWRGOOD. Once asserted, THERMTRIP# remains asserted until PWRGOOD is de-asserted. The deassertion of PWRGOOD causes the deassertion of THERMTRIP#, but if the processor's junction temperature remains at or above the trip level, THERMTRIP# will be reasserted within 10μs of the assertion of PWRGOOD.
VID[5:0]Outputs. Voltage ID. See “Voltage Identification” on page 680.

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