Under some circumstances, an IA32 processor generates a Special transaction to broadcast a message to the platform. In other words, this is not a point-to-point transaction that targets a particular agent. As indicated earlier, every transaction requires a Response Agent, and the Root Complex is typically the Response Agent (i.e., the central agent) for the Special transaction. This transaction has the following characteristics:
Although the content of the address bus in Packet A is “don't care,” it is factored into the address parity on AP[1:0]#.
In Packet A, the request type issued on REQ[4:0]# is 01000b (this is the logical, not electrical, value).
Although the content of A[35:16]# and A[7:3]# in Packet B are “don't care,” it is factored into the address parity on AP[1:0]#.
In Packet B, the Byte Enables indicate the type of message being broadcast (see “The Message Types” on page 1306).
No data is transferred in the transaction and the No Data response is the appropriate response.
As stated in the previous section, the message type is driven out on BE[7:0]# (A[15:8]#) in Packet B. Table 54-1 on page 1306 indicates the types of messages that are currently defined.
BE[7:0]# | Message Type |
---|---|
00h | NOP. This message is broadcast by each of the processors during the selection of the BSP (i.e., the Boot Strap Processor). See “Boot Strap Processor (BSP) Selection” on page 885 for more information. |
01h | Shutdown. Indicates that the processor has incurred a severe software error. As with previous IA32 processors, the Pentium® 4 generates this message when it encounters a triple-fault condition. In other words, it has received another exception while attempting to call the Double-Fault exception handler. In response to the triple-fault, the processor ceases program execution and generates this message. Whether or not a system pays any attention to this message and, if so, the action taken by the system, is system design-specific. In a PC system, upon detecting this message, the Root Complex asserts reset to the system and then removes it. This causes the system to re-execute the POST. Refer to “Shutdown Mode” on page 303. |
02h | Flush. Generated by the processor when it executes an INVD (invalidate caches) instruction. This instruction causes the processor to invalidate all of its internal caches without writing modified lines back to memory. The processor then broadcasts this message on the FSB to inform any external caches that they should also invalidate their contents. It should be noted that this message does not cause other processors to invalidate their internal caches. If this is the programmer's intent, the processor's Local APIC should be instructed to send an IPI (Inter-Processor Interrupt message packet) to the other processors that commanding each of them to execute a small program that will cause each of them to dump their caches as well. |
03h | Halt. Generated by the processor when it executes the HLT instruction. Whether or not a system pays any attention to this message and, if so, the action taken by the system, is system design-specific. In a PC-based system, the North Bridge generates a PCI Special Cycle transaction and broadcasts the Halt message in the Data Phase of the PCI transaction (in case any of the PCI agents care that a processor has halted). |
04h | Sync. Generated by the processor when it executes an WBINVD (Write Back and Invalidate caches) instruction. This instruction causes the processor to first write back all modified lines to memory, after which it invalidates all of its internal caches. The processor then broadcasts this message on the FSB to inform any external caches that they should do the same. It should be noted that this message does not cause other processors to take this action in their internal caches. If this is the programmer's intent, the processor's Local APIC should be instructed to send an IPI (Inter-Processor Interrupt message packet) to the other processors commanding each of them to execute a small program that will cause each of them to dump their caches as well. |
05h | Flush Acknowledge. When the chipset asserts the processor's FLUSH# input (note that this input was eliminated on the Pentium® 4), this causes the processor to first write back all modified lines to memory, after which it invalidates all of its internal caches. The processor then broadcasts this message to inform system logic that it has completed the operation. |
06h | Stop Grant Acknowledge. When the chipset asserts the processor's STPCLK# (Stop Clock) input, the processor turns off the clock to all of its internal units with the exception of its FSB interface, the Time Stamp Counter (TSC), and the APIC. This is referred to as the Stop Grant state and greatly diminishes the processor's power consumption. In addition, this message is broadcast on the FSB to inform the system that the Stop Clock request has been honored. |
07h | SMI Acknowledge. In response to a System Management Interrupt received on SMI# (or via the Local APIC), the processor takes the following steps:
|
08h-FFh | Reserved. |
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