Error Observation Options

The processor may be configured to monitor or to ignore two of its error inputs that are used to signal errors during FSB transactions. Those two inputs are:

• MCERR# (Machine Check Error). Sampling A9# low at the trailing-edge of reset configures the processor to monitor MCERR#, while sampling it high configures the processor to ignore MCERR#. This is referred to as the processor's MCERR# observation policy. A detailed discussion of MCERR# may be found in the MCERR# entry in Table 55-1 on page 1314, in “The Request Phase Parity” on page 1204, in “The Response Phase Parity” on page 1268, and in “Data Bus Parity” on page 1270.

• BINIT# (Bus Initialization). Sampling A10# low at the trailing-edge of reset configures the processor to monitor BINIT#. Sampling A10# high configures the processor to ignore BINIT#. This is referred to as the processor's BINIT# observation policy. A detailed discussion of BINIT# may be found in the BINIT# entry of Table 55-1 on page 1314.