Events that Initiate a Task Switch
There are a number of events that can cause the processor to suspend the current task and start or resume another task. Table 11-1 on page 192 provides a description of each event. The sections that follow detail the sequence of actions taken by the processor when suspending the current task and starting or resuming another one.
| Event | Description |
|---|---|
| Far CALL/Far jump to TSS descriptor | If the 16-bit segment portion of a far jump or far CALL selects a TSS descriptor in the GDT, a task switch occurs. The offset portion of the target address is discarded. The processor loads the 16-bit segment selector into the visible portion of the TR and then loads the selected TSS descriptor from the GDT into the invisible part of the TR. A privilege check is performed and, if the currently executing program has sufficient privilege (CPL ≤ DPL), the state of the current task is stored in its TSS and the register values from the new TSS (identified by the TSS descriptor) are loaded into the processor's register set. More detailed information can be found in the sections entitled “Switch as a Result of a Far Call” on page 197 and “Switch as the Result of a Far Jump” on page 197. |
| Far CALL/Far jump to Task Gate descriptor | All TSS descriptors must reside in the GDT. The DPL of a TSS descriptor is typically set to zero. This means that a program that resides at a less-privileged level could not switch to the task defined by the TSS. If the currently executing program has access to a Task Gate in its LDT, it can switch to a task (if the less-privileged of the currently executing program's CPL and RPL is at least as privileged as the Task Gate's DPL). The TSS DPL is ignored. The Task Gate has the format specified in Figure 11-1 on page 195 and is described in the section entitled “Task Gate Descriptor” on page 194. Also refer to the sections entitled “Switch as a Result of a Far Call” on page 197 and “Switch as the Result of a Far Jump” on page 197. |
| INT nn execution that selects a Task Gate in IDT | When the processor executes an INT nn instruction, the value nn acts as an index into the IDT. If the selected IDT entry contains a Task Gate descriptor and the program executing the INT instruction has sufficient privilege, a task switch results. Additional information can be found in the sections entitled “Task Gate Descriptor” on page 194 and “Switch Due to a BOUND/INT/INTO/INT3 Instruction” on page 198, and in the chapter entitled “Interrupts and Exceptions” on page 251. |
| Hardware interrupt that selects a Task Gate in IDT | When a hardware interrupt request is detected by the processor, the interrupt vector obtained from the interrupt controller is used as an index into the IDT. If the selected IDT entry contains a Task Gate descriptor, a task switch results (exceptions, interrupts and IRET cause a task switch regardless of the Task Gate's DPL). Additional information can be found in the sections entitled “Task Gate Descriptor” on page 194 and “Task Switch Details” on page 196, and in the chapter entitled “Interrupts and Exceptions” on page 251. Also refer to “Scheduler Causes a Task Switch” on page 172. |
| Software exception that selects a Task Gate in IDT | When a software exception condition is detected by the processor, the type of exception condition determines the index into the IDT. If the selected IDT entry contains a Task Gate descriptor, a task switch results (exceptions, interrupts and IRET cause a task switch regardless of the Task Gate's DPL). Additional information can be found in the sections entitled “Switch Due To an Interrupt or Exception” on page 196 and “Task Switch Details” on page 196, and in the chapter entitled “Interrupts and Exceptions” on page 251. |
| IRET execution with EFlags[NT] bit set | Refer to the sections entitled “Link Field (to Old TSS Selector)” on page 184 and “Linked Tasks” on page 201 for a detailed description. |
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