Introduction to the Descriptor Tables

Segment Descriptors Reside in Memory

Whenever the programmer attempts to access a new memory segment (by loading a value into the respective segment register), the processor reads the indicated segment descriptor from memory into a special segment descriptor cache register within the processor. From that point forward, the processor has instant access to the base address, length and other attributes related to that segment.

There are three types of descriptor tables:

• Global Descriptor Table (GDT). Describes segments of memory that are global to all programs. There is only one GDT.

• Local Descriptor Tables (LDTs). A particular OS may not implement any LDTs, only one LDT for all tasks, or a separate LDT for each task. Ideally, the OS would implement a separate LDT for each task. The entries in the LDT describe segments of memory local to the currently executing task.

• Interrupt Descriptor Table (IDT). There is only one IDT. The entries in the IDT describe interrupt and exception handlers and their respective access rights.

The GDT and LDTs are described in this chapter, while the IDT is described in the chapter entitled “Interrupts and Exceptions” on page 251.

Global Descriptor Table (GDT)

GDT Description

The OS sets up and maintains one GDT. It is illustrated in Figure 7-4 on page 116, and may contain as many as 8192d entries (note that entry zero is not used).

There can be five possible types of descriptors in the GDT:

TSSs and Task Gates are described in the chapter entitled “Creating a Task” on page 171. LDTs are described in the section entitled “Local Descriptor Tables (LDTs)” on page 116. Procedure Call Gates are described in the section entitled “Calling a Procedure in the Current Task” on page 142. Code, data and stack segments are described in:

• the chapter entitled “Code Segments” on page 133.

• the section entitled “The Data Segments” on page 158.

• the section entitled “Selecting and Accessing a Stack Segment” on page 161.

Setting the GDT Base Address and Size

The OS kernel is responsible for creating and maintaining the GDT in memory. Once created in memory, the OS kernel tells the processor the base address and size of the GDT. This is accomplished using the LGDT (Load GDT Register) instruction. When executed, six bytes of information are read from memory starting at the specified memory address and are placed in the processor's GTDR (see Figure 7-4 on page 116). The information loaded into the GDTR consists of a 16-bit limit (indicating the size of the GDT) plus a 32-bit base address for the table. At a maximum, the table can contain 8192d entries (minus one, because entry zero is unused), each eight bytes long, for a maximum table length of 64KB.

GDT entry zero is unused for a good reason. This permits the programmer to place the null value of zero into any of the data segment registers without causing an exception (e.g., when initializing the register set). This selects entry zero in the GDT. The processor does not actually access GDT entry zero.

Local Descriptor Tables (LDTs)

Optimally, the OS programmer can define a set of memory segments for each separate task. The segments local to (i.e., owned by) a task are defined in the task's LDT in memory (see Figure 7-8 on page 121). The GDT must contain an LDT descriptor for each LDT. An LDT descriptor in the GDT defines an LDT's base address and size. Figure 7-5 on page 118 illustrates the relationship of the GDT entries to the LDTs.

The LDT to be used by the currently executing program may be selected in either of two ways:

• The OS may programmatically load a GDT segment selector into the processor's LDTR by executing the LLDT instruction.

• Whenever the processor switches to a new task, it automatically reads the GDT segment selector into the LDTR from the new task's TSS (Task State Segment). A detailed description of task switching can be found in “Creating a Task” on page 171 and “Mechanics of a Task Switch” on page 191.

The visible and invisible parts of the LDTR are pictured in Figure 7-6 on page 119. The Requestor Privilege Level (RPL) is discussed in the chapters entitled “Code Segments” on page 133 and “Data and Stack Segments” on page 157. A Table Indicator (TI) value of zero tells the processor to access the GDT and the index value in bits [15:3] tells the processor which of the 8192d entries in the GDT to read. To access the indicated entry, the processor performs the following series of actions:

From this point forward, the processor has immediate on-chip access to the base address, size and attributes of the currently executing task's LDT. Figure 7-7 on page 120 illustrates the format of a Local Descriptor Table entry in the GDT. Since an LDT is considered to be an OS segment, the System bit must be cleared to zero. The remainder of the fields in the descriptor are defined later in this chapter (in the section entitled “General Segment Descriptor Format” on page 121).

The LDT for the currently executing task may contain:

• Code, data and stack segment descriptors for memory segments local to this task.

• Procedure Call Gates that permit the currently executing task to call procedures residing in code segments of a higher privilege level.

• Task Gates that permit the currently executing task to execute another task.