Processor Core Speed Selection

A Phase-Locked Loop (PLL) within the processor multiplies the Bus Clock (CLK) frequency (supplied by the system board's clock generator) to produce the processor's internal clock that drives all of its internal units. On the early members of the P6 processor family, the processor sampled four of its inputs on the trailing-edge of reset to determine the multiplication factor to use. People who wanted to overclock a processor would manipulate the values presented to the processor on these four inputs to select a higher multiplication factor than that warantied by Intel®.

Starting with the later members of the P6 processor family and continuing with all members of the Pentium® 4 processor family, this is no longer the case. See Figure 36-9 on page 868. Instead, two processor outputs, BSEL[1:0], tell the system board's clock generator what frequency BCLK must be supplied to the processor. The processor then uses a hardwired multiplier value to produce the internal clock.