The MSRs

Table 56-2 on page 1347 identifies the MSRs implemented in the Pentium® 4 and Pentium® M processors. Starting with the Pentium® 4, all MSRs in the table with shaded register names (and starting with “IA32_”) are defined as part of the IA32 architecture and, as such, are guaranteed to be implemented at the same MSR addresses in future IA32 processors.

Table 56-2. Pentium® 4 and Pentium® M MSRs
ECX = Reg Address before executing RDMSR or WRMSR)Register Name1st inDescription
HexDecimal
Miscellaneous MSRs
000h0IA32_P5_MC_ADDRP5Please note that, although these are Pentium®-specific MSRs, access attempts in all post-Pentium® processors do not cause an exception.
001h1IA32_P5_MC_TYPE
010h16IA32_TSCThe Time Stamp Counter (TSC) register was introduced in the Pentium® and is present in all subsequent IA32 processors.
017h23IA32_PLATFORM_IDPIIIThis register was added in the Pentium® III as an aid to the Microcode update feature. For more information, refer to “MicroCode Update Feature” on page 631.
01Bh27IA32_APIC_BASEPro

  • This register permits the base memory address of the Local APIC's register set to be programmed.

  • It also permits the Local APIC to be enabled or disabled by software.

  • It contains the BSP bit.

See “Permanently Disabling the Local APIC” on page 1510 and “Introduction to the Local APIC's Register Set” on page 1524 for a detailed description of this register.
02Ah42MSR_EBC_HARD_ POWERONP4External Bus (FSB) Control Hard Power On register. See “Program-Accessible Startup Features” on page 869 for a detailed description of this read-only register.
02Bh43MSR_EBC_SOFT_ POWERONExternal Bus (FSB) Control Soft Power On register (R/W). Processor Soft Power-On Configuration. Enables and disables processor features. See “Program-Accessible Startup Features” on page 869 for a detailed description of this register.
02Ch44MSR_EBC_ FREQUENCY_IDRead-only. External Bus (FSB) Control Frequency ID Register. Processor Frequency Configuration. Indicates the speed at which the FSB's BCLK is running: Encoding Scalable Bus Speed

  • 000b=100MHz.

  • 001b = 133MHz.

  • 010b = 200MHz.

  • All other values are reserved.

1A0h416IA32_MISC_ENABLEEnable Miscellaneous Processor Features. (R/W) Allows a variety of processor functions to be enabled or disabled. See Figure 56-21 on page 1373 for more information.
1D9h473IA32_DEBUGCTLProThe DEBUGCTL register implements bits that control miscellaneous debug-related functions. See Figure 54-4 on page 1311 for more information.
0277h631IA32_CR_PATPIIPage Attribute Table. Note that the Intel® Volume 3: System Programming Guide, Order Number 245472-008, incorrectly refers the reader to a discussion of the Fixed-Range MTRRs for a description of this register. The PAT feature was first introduced in the Pentium® II Xeon processor. Refer to “PAT Feature (Page Attribute Table)” on page 797 for a detailed description of the PAT feature.
600h1536IA32_DS_AREAP4DS Save Area (RW). Points to the Debug Store buffer management area, which is used to manage the BTS and PEBS buffers. See “The Debug Store (DS) Mechanism” on page 1366 for a detailed description of this register.
Microcode Update MSRs
079h121IA32_BIOS_UPDT_TRIGProThe BIOS Update-related MSRs. See “MicroCode Update Feature” on page 631 for a detailed description of the Microcode Update feature.
08Bh139IA32_BIOS_SIGN
Performance Monitoring MSRs The Pentium® 4 processor increased the number of performance counters from 2 to 18. See “The Performance Monitoring Facility” on page 1371 for a detailed description of the Pentium® 4's Performance Monitoring facility.
300h768MSR_BPU_COUNTER0P4Performance Counters BPU = Branch Prediction Unit
301h769MSR_BPU_COUNTER1
302h770MSR_BPU_COUNTER2
303h771MSR_BPU_COUNTER3
360h864MSR_BPU_CCCR0Counter Control and Configuration Registers. BPU = Branch Prediction Unit
361h865MSR_BPU_CCCR1
362h866MSR_BPU_CCCR2
363h867MSR_BPU_CCCR3
3B2h946MSR_BPU_ESCR0ESCR = Event Select Control Registers BPU = Branch Prediction Unit
3B3h947MSR_BPU_ESCR1
304h772MSR_MS_COUNTER0Performance Counters MS = Microcode Store ROM
305h773MSR_MS_COUNTER1
306h774MSR_MS_COUNTER2
307h775MSR_MS_COUNTER3
364h868MSR_MS_CCCR0P4Counter Control and Configuration Registers. MS = Microcode Store ROM
365h869MSR_MS_CCCR1
366h870MSR_MS_CCCR2
367h871MSR_MS_CCCR3
3C0h960MSR_MS_ESCR0ESCR = Event Select Control Registers MS = Microcode Store ROM
3C1h961MSR_MS_ESCR1
308h776MSR_FLAME_COUNTER0Performance Counters FLAME = ?
309h777MSR_FLAME_COUNTER1
30Ah778MSR_FLAME_COUNTER2
30Bh779MSR_FLAME_COUNTER3
368h872MSR_FLAME_CCCR0Counter Control and Configuration Registers FLAME = ?
369h873MSR_FLAME_CCCR1
36Ah874MSR_FLAME_CCCR2
36Bh875MSR_FLAME_CCCR3
3A6h934MSR_FLAME_ESCR0ESCR = Event Select Control Registers FLAME = ?
3A7h935MSR_FLAME_ESCR1
30Ch780MSR_IQ_COUNTER0P4Performance Counters IQ = Instruction Queue
30Dh781MSR_IQ_COUNTER1
30Eh782MSR_IQ_COUNTER2
30Fh783MSR_IQ_COUNTER3
310h784MSR_IQ_COUNTER4
311h785MSR_IQ_COUNTER5
36Ch876MSR_IQ_CCCR0Counter Control and Configuration Registers. IQ = Instruction Queue
36Dh877MSR_IQ_CCCR1
36Eh878MSR_IQ_CCCR2
36Fh879MSR_IQ_CCCR3
370h880MSR_IQ_CCCR4
371h881MSR_IQ_CCCR5
3BAh954MSR_IQ_ESCR0ESCR = Event Select Control Registers IQ = Instruction Queue
3BBh955MSR_IQ_ESCR1
3A0h928MSR_BSU_ESCR0ESCR = Event Select Control Registers BSU = Bus Sequence Unit
3A1h929MSR_BSU_ESCR1
3A2h930MSR_FSB_ESCR0ESCR = Event Select Control Registers FSB = Front-Side Bus
3A3h931MSR_FSB_ESCR1
3A4h932MSR_FIRM_ESCR0ESCR = Event Select Control Registers FIRM = ?
3A5h933MSR_FIRM_ESCR1
3A8h936MSR_DAC_ESCR0P4ESCR = Event Select Control Registers DAC = Data cache Access Control unit
3A9h937MSR_DAC_ESCR1
3AAh938MSR_MOB_ESCR0ESCR = Event Select Control Registers MOB = Memory Order Buffer
3ABh939MSR_MOB_ESCR1
3ACh940MSR_PMH_ESCR0ESCR = Event Select Control Registers PMH = ?
3ADh941MSR_PMH_ESCR1
3AEh942MSR_SAAT_ESCR0ESCR = Event Select Control Registers SAAT = ?
3AFh943MSR_SAAT_ESCR1
3B0h944MSR_U2L_ESCR0ESCR = Event Select Control Registers U2L = ?
3B1h945MSR_U2L_ESCR1
3B4h948MSR_IS_ESCR0ESCR = Event Select Control Registers IS = ?
3B5h949MSR_IS_ESCR1
3B6h950MSR_ITLB_ESCR0ESCR = Event Select Control Registers ITLB = Instruction Translation Lookaside Buffer
3B7h951MSR_ITLB_ESCR1
3B8h952MSR_CRU_ESCR0ESCR = Event Select Control Registers CRU = Cache References Unit
3B9h953MSR_CRU_ESCR1
3CCh972MSR_CRU_ESCR2
3CDh973MSR_CRU_ESCR3
3E0h992MSR_CRU_ESCR4
3E1h993MSR_CRU_ESCR5
3BCh956MSR_RAT_ESCR0P4ESCR = Event Select Control Registers RAT = Register Alias Table
3BDh957MSR_RAT_ESCR1
3BEh958MSR_SSU_ESCR0ESCR = Event Select Control Registers SSU = ?
3C2h962MSR_TBPU_ESCR0ESCR = Event Select Control Registers TBPU = Type of mis-predicted branches by BPU
3C3h963MSR_TBPU_ESCR1
3C4h964MSR_TC_ESCR0ESCR = Event Select Control Registers TC = Trace Cache
3C5h965MSR_TC_ESCR1
3C8h968MSR_IX_ESCR0ESCR = Event Select Control Registers IX = ?
3C9h969MSR_IX_ESCR1
3CAh970MSR_ALF_ESCR0ESCR = Event Select Control Registers ALF = ?
3F0h1008MSR_TC_PRECISE_EVENTSee “Front-End Tagging” on page 1411.
3F1h1009IA32_PEBS_ENABLESee Figure 56-26 on page 1417.
3F2h1010MSR_PEBS_MATRIX_VERTSee “Replay Tagging” on page 1413.
Memory Type and Range Registers (MTRRs) They are optional in the architecture, but are implemented in the Pentium® Pro through the Pentium® 4 and Pentium® M. The MTRR registers permit the BIOS and/or the OS to define the rules of conduct that the processor must use when accessing various areas of memory. See “MTRRs Added” on page 572 for a detailed description of the MTRRs.
0FEh254IA32_MTRRCapProVariable-Range MTRRs.
200h512IA32_MTRR_PHYSBASE0
201h513IA32_MTRR_PHYSMASK0
202h514IA32_MTRR_PHYSBASE1
203h515IA32_MTRR_PHYSMASK1
204h516IA32_MTRR_PHYSBASE2
205h517IA32_MTRR_PHYSMASK2
206h518IA32_MTRR_PHYSBASE3
207h519IA32_MTRR_PHYSMASK3
208h520IA32_MTRR_PHYSBASE4
209h521IA32_MTRR_PHYSMASK4Pro
20Ah522IA32_MTRR_PHYSBASE5
20Bh523IA32_MTRR_PHYSMASK5
20Ch524IA32_MTRR_PHYSBASE6
20Dh525IA32_MTRR_PHYSMASK6
20Eh526IA32_MTRR_PHYSBASE7
20Fh527IA32_MTRR_PHYSMASK7
250h592IA32_MTRR_FIX64K_00000 Fixed-Range MTRRs.
258h600IA32_MTRR_FIX16K_80000 
259h601IA32_MTRR_FIX16K_A0000 
268h616IA32_MTRR_FIX4K_C0000 
269h617IA32_MTRR_FIX4K_C8000 
26Ah618IA32_MTRR_FIX4K_D0000 
26Bh619IA32_MTRR_FIX4K_D8000 
26Ch620IA32_MTRR_FIX4K_E0000 
26Dh621IA32_MTRR_FIX4K_E8000 
26Eh622IA32_MTRR_FIX4K_F0000 
26Fh623IA32_MTRR_FIX4K_F8000 
2FFh767IA32_MTRR_DEF_TYPE MTRR Default Type register.
MCA Registers See “The Machine Check Architecture” on page 1363 for a detailed description of the Pentium® 4's implementation of the MCA.
179h377IA32_MCG_CAPProMC Global Count and Present register.
17Ah378IA32_MCG_STATUSMC Global Status register. Note: In the Intel® Volume 3: System Programming Guide, Order Number 245472-008, this register is erroneously called IA32_STATUS.
17Bh379IA32_MCG_CTLMC Global Control register. Note: In the Intel® Volume 3: System Programming Guide, Order Number 245472-008, this register is erroneously called IA32_CTL.
180h384IA32_MCG_EAXP4Machine Check EAX Save State.
181h385IA32_MCG_EBXMachine Check EBX Save State.
182h386IA32_MCG_ECXMachine Check ECX Save State.
183h387IA32_MCG_EDXMachine Check EDX Save State.
184h388IA32_MCG_ESIMachine Check ESI Save State.
185h389IA32_MCG_EDIMachine Check EDI Save State.
186h390IA32_MCG_EBPMachine Check EBP Save State.
187h391IA32_MCG_ESPMachine Check ESP Save State.
188h392IA32_MCG_EFLAGSMachine Check EFLAGS Save State.
189h393IA32_MCG_EIPMachine Check EIP Save State.
18Ah394IA32_MCG_MISCP4This register contains only one bit (DS). When set to one, it indicates that a Page Fault or a Page Assist occurred during a Debug Store operation. Refer to “The Debug Store (DS) Mechanism” on page 1366 for a detailed description of the DS facility.
400h1024IA32_MC0_CTLProMCA Bank 0 error logging registers.
401h1025IA32_MC0_STATUS
402h1026IA32_MC0_ADDR
403h1027IA32_MC0_MISCP4Bank 0 Miscellaneous register. Defined as optional in the MCA architecture but is implemented in the Pentium® 4 family processors.
404h1028IA32_MC1_CTLProMCA Bank 1 error logging registers. The MISC register is defined as optional in MCA architecture but is implemented in the Pentium® 4 family processors.
405h1029IA32_MC1_STATUS
406h1030IA32_MC1_ADDR
407h1031IA32_MC1_MISCP4
408h1032IA32_MC2_CTLProMCA Bank 2 error logging registers. The MISC register is defined as optional in MCA architecture but is implemented in the Pentium® 4 family processors.
409h1033IA32_MC2_STATUS
40Ah1034IA32_MC2_ADDR
40Bh1035IA32_MC2_MISCP4
40Ch1036IA32_MC3_CTLProMCA Bank 3 error logging registers. The MISC register is defined as optional in MCA architecture but is implemented in the Pentium® 4 family processors.
40Dh1037IA32_MC3_STATUS
40Eh1038IA32_MC3_ADDR
40Fh1039IA32_MC3_MISCP4
Branch Recording Registers
1DAh474MSR_LASTBRANCH_TOSP4Last Branch Record Stack TOS. (RO) Contains an index (0, 1, 2, or 3) that points to the top of the last branch record stack (that is, that contains the index of the MSR containing the most recent branch record). See the next row.
1DBh475MSR_LASTBRANCH_0The Branch Recording registers. See “Last Branch, Interrupt, and Exception Recording” on page 1365 for a detailed description of the Pentium® 4's Branch Recording facility.
1DCh476MSR_LASTBRANCH_1
1DDh477MSR_LASTBRANCH_2
1DEh478MSR_LASTBRANCH_3
Fast System Enter/Exit Registers
174h372IA32_SYSENTER_CSPIICS register target for CPL 0 code. See “Fast System Call/Return Instruction Pair” on page 708.
175h373IA32_SYSENTER_ESPStack pointer for CPL 0 stack.
176h374IA32_SYSENTER_EIPCPL 0 code entry point.
Thermal Monitor related Registers (refer to “The Thermal Monitoring Facilities” on page 1340 for a complete description of the Thermal Monitoring facility).
19Ah410IA32_THERM_CONTROLP4Thermal Monitor Control. (RW) Enables and disables on-demand clock modulation and allows selection of the on-demand clock modulation duty cycle.
19Bh411IA32_THERM_INTERRUPTThermal Interrupt Control. (RW) Enables and disables the generation of an interrupt on temperature transitions detected by the processor's thermal sensor and thermal monitor.
19Ch412IA32_THERM_STATUSThermal Monitor Status. (RW) Contains status info about the processor's thermal sensor and automatic thermal monitoring facilities.
Last Exception Recording Registers
1D7h471MSR_LER_FROM_LIPP4Last Exception Record From and To Linear EIP. (RO). Contains the pointers to:

  • The last branch instruction that the processor executed prior to the last exception that was generated or the last interrupt that was handled.

  • The target of that branch instruction.

1D8h472MSR_LER_TO_LIP

Figure 56-26. The IA32_PEBS_Enable MSR

[View full size image]

All MSRs whose names do not start with “IA32_” are processor design-specific and are not part of the IA32 architecture spec.

Please be aware that the author has chosen to group the MSRs by function rather than listing them in ascending address order as the Intel® documentation does.

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