Soft Reset (INIT#)
The Pentium® was the first IA32 processor to implement the INIT# (Initialization) input pin. This is effectively a soft reset to the processor.
Hot Reset and 286 DOS Extender Programs
MS-DOS was written specifically for the 8088 processor using 8088-specific instructions. Since the 8088 only implemented 20 address signal pins, it was incapable of generating a memory address greater than FFFFFh, or 1MB. Furthermore, Protected Mode wasn't introduced until the advent of the 286 processor. Consequently, MS-DOS could only address the lower 1MB and had no concept of Protected Mode.
When a 286 was powered up, it initially operated in Real Mode. In other words, it operated as if it were an 8088. Among other things this meant that, although the 286 had 24 address output pins and could therefore physically address up to 16MB of memory address space, it was limited to the lower 1MB when in Real Mode.
Many MS-DOS application programs required access to more memory space than allowed under MS-DOS. As an example, many Lotus 1-2-3 spreadsheets required very large amounts of memory space, well in excess of that allowed under MS-DOS and the 8088 processor.
On a system based on the 286, the application program accomplished an access to extended memory by calling a special device driver (typically referred to as a 286 DOS Extender program) that, when called, accomplished the following steps:
1. | The driver prepared the segment descriptor tables in memory prior to switching the processor into Protected Mode. |
2. | The driver also saved the address of the next instruction to be executed when the processor was subsequently returned to Real Mode. |
3. | The driver then switched the 286 into Protected Mode and accessed extended memory above 1MB on behalf of the application program that called it (for example, to store spreadsheet data). |
4. | Once the extended memory access was completed, the driver had to switch the processor back into Real Mode. Here's where the problem came in. In order to switch the 286 from Protected to Real Mode, the processor had to be reset. |
To do this, the following actions had to be taken:
The programmer stored an address pointer in memory that pointed to the entry point of the Real Mode routine that was responsible for restoring the system to its previous operating condition (prior to the calling of the DOS extender program). This pointer was stored in locations 0040:0067 to 0040:006A in the BIOS Data Area.
A special value (05h or 0Ah) was stored in configuration CMOS RAM location 0Fh (sometimes referred to as the Reset Code Byte location) to indicate the reason for the reset. Refer to Table 20-4 on page 488 for the definition of the Reset Code Byte in CMOS RAM.
Table 20-4. Reset Code Byte Values Value Description 00h Normal Power-Up reset or Ctrl-Alt-Del reset depending on the value of the Reset flag in memory at location 0040:0072 and 0040:0073 of the BIOS Data Area. When the Reset flag contains the value 1234h, the POST memory test is skipped. 04h POST is skipped. Causes the OS to be loaded from disk. 05h POST is skipped and memory preserved. The 286 processor could not be switched from Protected Mode into Real Mode without resetting the processor. This presented problems when the programmer wished to temporarily switch to Protected Mode to access extended memory and then switch back into Real Mode to continue execution. When a program had to temporarily leave Real Mode and enter Protected Mode, the programmer first stored a four byte memory address (pointer) into memory starting at 0040:0067. This pointer specifies the address at which real mode execution will resume. Having done so, the program could then switch the processor into Protected Mode and access extended memory. Upon completing the extended memory access, the programmer had to place the value 05h or 0Ah into the Reset Code byte in CMOS RAM and then reset the 286. When reset is deasserted, the processor is in Real Mode and begins executing the POST. The POST code checks for a 05h or a 0Ah in the Reset Code byte, and, if present, jumps to the memory address specified in memory starting at location 0040:0067 to resume execution. In addition, if the Reset Code byte value is 05h, an EOI command is issued to the Interrupt Controller. 09h Block-move return. This value is placed in the reset code byte by a BIOS call using INT 15h to move a block of information between conventional and extended memory. In order to accomplish this move, the processor must switch into Protected Mode. On a 286-based system, the INT 15h routine sets the reset code byte to 09h prior to resetting the processor to return to Real Mode after the block move. After being reset, the processor starts executing the POST, checks the Reset Code byte value, and then executes an interrupt return (IRET) instruction to return to the original program after completion of the call to the INT 15h BIOS routine. 0Ah Jump to the Real Mode pointer stored in memory starting at 0040:0067 without issuing an EOI to the Interrupt Controller. See the explanation for Reset Code byte = 05h. When reset was asserted and then deasserted, the processor began to fetch and execute instructions at the power-on restart address exactly as if a power up had just occurred.
At the beginning of the POST, the programmer reads the Reset Code Byte value stored in configuration RAM to ascertain the reset's cause. In this case, the value (05h or 0Ah) indicates that it was caused by Hot Reset to get back to Real Mode and continue execution of the DOS application that had called the DOS extender program.
The POST code then retrieved the previously stored Real Mode address pointer found at locations 0040:0067 through 0040:006A and jumped to the indicated address and resumed where it left off in the DOS application.
Note that most system board vendors employ a Hot Reset “intercept” where logic between the processor and the Keyboard/Mouse Controller detects a FEh written to the Keyboard controller and immediately generates a Fast Hot Reset to the processor. This provides faster pulsing of the processor's reset signal compared to the slower generation via a command to the Keyboard controller. Later versions of Intel®'s microcontrollers (typically used as keyboard controllers) provide an internal intercept that results in the generation of Fast Hot Reset.
Alternate (Fast) Hot Reset
The Alternate or Fast Hot Reset command can be issued to System Control Port A at IO address 0092h (sometimes called the PS/2 compatibility port). Alternate Hot Reset performs the same function as the Hot Reset command. However, the processor is reset more quickly using this method than when using Hot Reset. If the Hot Reset command is issued to the Keyboard/Mouse Controller, it must be interpreted by the ROM-based program inside of the controller, while the Alternate Hot Reset signal is pulsed much more quickly by the hardware.
Alternate Hot Reset is generated by writing a one to bit 0 of System Control Port A. This generates a pulse on the Alternate Hot Reset signal line which, in turn, causes a pulse on the Hot Reset signal. This resets the processor.
286 DOS Extenders on Post-286 Processors
If a DOS Extender program written for the 286 is executed on a system with a post-286 processor, things must be handled a little differently. The system board logic is designed so that the Hot Reset signal line is attached to the processor's INIT# input rather than to its RESET# input.
While the assertion of the INIT# signal does cause the processor to start fetching from the power on restart address, it exhibits the following differences from the assertion of RESET#:
The code cache retains its contents.
The data cache retains its contents.
The processor's posted memory write buffers retain their contents.
The FP registers retain their contents.
The model-specific registers (MSRs) retain their contents.
CR0[CD] and CR0[NW] are unchanged.
The processor resets its integer registers to their default values.
The processor continues to handle the snooping of memory transactions initiated by other FSB entities while INIT# is asserted.
In other words, the POST begins executing, but the processor does not lose any of the code or data that it worked so hard to collect in its caches, nor does it lose any data operands currently in its FP data registers.