The Previous Part
The previous part provided a detailed description of the hardware design and software enhancements encompassed in the Pentium® 4 processor family. It consists of the following chapters:
“Pentium® 4 Road Map” on page 813.
“Pentium® 4 System Overview” on page 823.
“Pentium® 4 Processor Overview” on page 835.
“Pentium® 4 PowerOn Configuration” on page 855.
“Pentium® 4 Processor Startup” on page 875.
“Pentium® 4 Core Description” on page 897.
“Hyper-Threading” on page 965.
“The Pentium® 4 Caches” on page 1009.
“Pentium® 4 Handling of Loads and Stores” on page 1061.
“The Pentium® 4 Prescott” on page 1091.
“Pentium® 4 FSB Electrical Characteristics” on page 1115.
“Intro to the Pentium® 4 FSB” on page 1137.
“Pentium® 4 CPU Arbitration” on page 1149.
“Pentium® 4 Priority Agent Arbitration” on page 1165.
“Pentium® 4 Locked Transaction Series” on page 1177.
“Pentium® 4 FSB Blocking” on page 1189.
“Pentium® 4 FSB Request Phase” on page 1201.
“Pentium® 4 FSB Snoop Phase” on page 1225.
“Pentium® 4 FSB Response and Data Phases” on page 1241.
“Pentium® 4 FSB Transaction Deferral” on page 1277.
“Pentium® 4 FSB IO Transactions” on page 1295.
“Pentium® 4 FSB Central Agent Transactions” on page 1301.
“Pentium® 4 FSB Miscellaneous Signals” on page 1313.
“Pentium® 4 Software Enhancements” on page 1321.
“Pentium® 4 Xeon Features” on page 1421.
This Part
This part describes the hardware and software characteristics of the Pentium® M processor and consists of the following chapter:
“Pentium® M Processor” on page 1425.
The Next Part
The next part provides a detailed description of processor identification, System Management Mode, and the IO and Local APICs. It consists of the following chapters:
“CPU Identification” on page 1443.
“System Management Mode (SMM)” on page 1463.
“The Local and IO APICs” on page 1497.
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