Machine Check Architecture (MCA)

The MCA feature was first implemented in the Pentium® processor and is present in all IA32 processor subsequent to the Pentium®. However, the MCA register set was greatly expanded starting with the Pentium® Pro processor. The Pentium®'s MCA consists of the following elements:

• The Machine Check exception. If enabled to do so, this exception is generated when the processor detects hardware errors that generally fall within the following categories:

  - FSB transaction errors.

  - Both correctable and uncorrectable ECC errors detected on internal caches or on the FSB.

  - Parity errors detected on the FSB or on internal ROM devices (such as the processor's Microcode ROM).

  - Storage errors in the processor's internal caches or TLBs.

• CR4[MCE] (see Figure 21-6 on page 497). This bit disables (0) or enables (1) the processor's ability to generate a Machine Check exception (exception 18d, or 12h). CR4[MCE] = 0 after reset.

• The Machine Check register set.

The Pentium®'s implementation of the MCA was quite primitive. The MCA register set consisted of only two registers:

• The MC Address Register, or MCAR (see Figure 21-10 on page 505).

  Figure 21-10. Machine Check Address Register (MCAR)

  

• The MC Type Register, or MCTR (see Figure 21-11 on page 505).

  Figure 21-11. Machine Check Type Register (MCTR)

  

The only Machine Check hardware errors the Pentium® could detect were related to errors in a FSB transaction. The Machine Check logic could not log any errors related to internal processor hardware failures.

An error in a FSB transaction fell into one of two categories:

• The detection of a data parity error during a read transaction on the FSB. This occurred only when the processor sampled its PEN# signal asserted during a given read FSB transaction. When asserted by the platform logic, PEN# instructed the processor to latch the contents of the address bus and FSB transaction type signals associated with the transaction.

• The processor's BUSCHK# input was sampled asserted at the end of a FSB transaction, indicating that the transaction was not completed successfully. The processor latched the address and transaction type into the Machine Check registers, and, if enabled to do so, the Machine Check exception was generated.

The Machine Check registers were introduced in the Pentium® and are read using the RDMSR (Read Model Specific Register) instruction. The MCAR contained the physical address present on the address bus during the failed transaction. The MCTR indicated the type of transaction that failed. MCTR[CHK] = 1 if the MCTR and MCAR contained valid information.