The FSB Characteristics

Uses the Pentium® 4 FSB Protocol

The FSB uses the same protocol as the Pentium® 4 processor family. The BCLK speed is 100MHz (rather than 200MHz as on the Pentium® 4). The address bus width is 32 bits consisting of A[31:3]# (rather than 36 bits as on the Pentium® 4's FSB).

Pentium® M-Specific Signals

The signals in Table 58-1 on page 1428 are specific to the Pentium® M processor (i.e., they are not found on the Pentium® 4 family processors).

Table 58-1. Pentium® M-Specific Signals
SignalInput/OutputDescription
PSI#Output

Power Status Indicator. Asserted when the processor is in the Deep Sleep or Deeper Sleep power management state. Asserted upon Deep Sleep entry and deasserted upon exit. PSI# can be provided as an input to the voltage regulator on the system board. When the processor asserts PSI#, the voltage regulator can use it to improve its light load efficiency (resulting in platform power savings). PSI# can also be used to simplify the design of the voltage regulator (it removes the need for the integrated 100μs timer required to mask the PWRGOOD signal during Deeper Sleep transitions). It also reduces the PWRGOOD monitoring requirements while the processor is in the Deeper Sleep state.

DPSLP#Input

Deep Sleep. When asserted to the processor by the chipset, this signal causes the processor to transition from the Sleep state to the Deep Sleep state (resulting in greater power savings). The chipset deasserts DPSLP# to return the processor to the Sleep state.

DPWR#Input

Data Bus Power. When asserted to the processor by the chipset, the processor's data bus input buffers are deactivated to conserve power. The MCH deasserts DPWR# when data bus activity is detected, thereby re-enabling the processor's data bus input receivers.


FSB Power Utilization Enhancements

The processor design implements the following FSB power-related changes:

  • The FSB uses lower LVS (Low Voltage Swing) levels than earlier FSB versions. Vref is 2/3 of Vcc and Vcc is quite low.

  • The processor incorporates on-die termination resistors for the FSB AGTL+ signals. Whenever any agent drives a signal low, the processor automatically disables its on-die termination resistor to save on power.

  • DPWR# (Data Bus Power) input. This signal is described in Table 58-1 on page 1428.

  • BPRI# input. When the processor doesn't need the bus (its BR0# output is not asserted) and no Priority Agent needs the bus (the processor's BPRI# input is deasserted), the processor disables its address bus inputs and its control inputs to conserve power. They are automatically re-enabled when the processor or a Priority Agent needs the bus (i.e., the processor detects BPRI# asserted by the chipset).

  • The address bus width is 32-bits (rather than 36 bits) wide because laptops typically do not need to address more than 4GB of memory. A side-benefit, however, is that it takes less power to drive a narrower address bus.

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