Instruction Set Changes

Eight new instructions were added to the 386 instruction repertoire:

• Exchange and Add (XADD) instruction (see “Exchange and Add (XADD)” on page 457).

• Compare and Exchange (CMPXCHG) instruction (see “Compare and Exchange (CMPXCHG)” on page 457).

• Invalidate Cache (INVD) instruction (see “Invalidate Cache (INVD)” on page 457).

• Write Back and Invalidate (WBINVD) instruction (see “Write Back and Invalidate (WBINVD)” on page 458).

• Invalidate TLB Entry (INVLPG) instruction (see “Invalidate TLB Entry (INVLPG)” on page 458).

• Resume from System Management Mode (RSM) instruction (see “Resume from System Management Mode (RSM)” on page 458).

• The CPUID instruction made its first appearance in the Pentium® processor and was also implemented in the later versions of the 486 (as well as all subsequent IA32 processors). A complete description of this instruction can be found in “CPU Identification” on page 1443.

• Byte Swap (BSWAP) instruction (see “Byte Swap (BSWAP)” on page 459).

Exchange and Add (XADD)

This instruction can be used to optimize parallel loop execution. When executed, it exchanges the destination operand with the source operand and then loads the sum of the two values into the destination operand. The destination operand can be a register or a memory location. The source operand is a register. When used with the LOCK prefix, it's executed as an atomic read/modify write (RMW) operation.

Compare and Exchange (CMPXCHG)

This instruction is intended for use in testing and manipulating software semaphores. It compares the value in AL, AX, or EAX with the destination operand. If the two values are equal, the source operand is loaded into the destination operand. Otherwise, the destination operand is loaded into AL, AX, or EAX. When used with a LOCK prefix, it's executed as an atomic read/modify write (RMW) operation. The destination operand receives a write without regard to the comparison's result (the processor never performs a locked read without subsequently performing a locked write). The destination operand is written back if the comparison fails. Otherwise, the source operand is written into the destination.

Invalidate Cache (INVD)

When this instruction is executed, all lines in the cache(s) are invalidated (including modified lines in the version of the 486 that implemented a write back cache). In addition, the processor executes the FLUSH version of the Special transaction on the FSB to command an external cache to invalidate its contents as well (including any modified lines). When executed on a post-486 processor, it causes the lines in all of the processor's caches to be invalidated followed by the performance of the FLUSH version of the Special transaction on the FSB to command an external cache to invalidate its contents as well (including any modified lines)

Write Back and Invalidate (WBINVD)

When this instruction is executed, the following actions take place:

• All modified lines in the internal cache(s) are written to system memory over the FSB.

• The internal cache(s) is invalidated.

• The Sync version of the Special transaction is performed on the FSB to command any external cache (if present) to write all modified lines back to memory.

• The FLUSH version of the Special transaction is performed on the FSB to command an external cache to invalidate its contents.

Invalidate TLB Entry (INVLPG)

When this instruction is executed, a lookup is performed in the TLB (Translation Lookaside Buffer) using the programmer-supplied 32-bit linear memory address. The selected PTE is invalidated in the TLB.

Resume from System Management Mode (RSM)

This instruction was introduced on the 386SL, but did not become a mainstream feature until the advent of the 486. When executed, it causes the processor to exit SMM and return to normal operation. The processor takes the following actions when executing an RSM instruction:

• It flushes all entries currently posted in its posted memory write buffers.

• It restores the contents of the processor's register set from the state-save map in SM memory, returning the processor to its state prior to SMI# being recognized.

• It deasserts the SMIACT# signal to re-enable access to normal memory.

• It resumes fetching and executing instructions from system memory.

Refer to “System Management Mode (SMM)” on page 1463 for a complete description of SMM.

Byte Swap (BSWAP)

When this instruction is executed, it causes the processor to reverse the byte order in the specified 32-bit register. When data is transferred between a register and memory by an IA32 processor, the order used is always little-endian. Software written for the VAX also used the little-endian methodology. Since some processor types (e.g., PowerPC and Power) store data in the reverse order (big-endian), the BSWAP instruction can be used to reorder data to allow efficient access to existing databases built on big-endian machines.