The WCBs Were Enhanced

For a complete description of the Write Combining memory type and the WCBs, refer to “The Memory Types” on page 581.

The Pentium® Pro and Pentium® II processors had four cache line fill buffers to handle the data returned from FSB line reads caused by cache misses. At a given moment in time, one of the fill buffers could be used as a WCB.

The Pentium® III design also implements four cache line fill buffers, but it can use any or all of them, when necessary, as WCBs. Of course, any of the buffers awaiting cache line data from outstanding FSB memory transactions cannot be used as WCBs. Conversely, any of the buffers currently in use as WCBs could not be used to accept cache line fill data from memory.

While the Pentium® Pro and Pentium® II processors required a dead cycle between back-to-back FSB dumps of the one and only WCB, the dead cycle requirement was eliminated on the Pentium® III.

While a full WCB on the earlier P6 processors was only dumped on the occasion of a synchronizing event (see “Forcing a Buffer Drain” on page 1083), a memory write to a different line of WC memory, or a on cache line fill request when the other three fill buffers were already in use, a Pentium® III WCB is dumped under the following circumstances:

• On the occasion of a synchronizing event (see “Forcing a Buffer Drain” on page 1083).

• Automatically when a WCB becomes full (this was a new feature in the Pentium® III).

• On the execution of an SFENCE (Store Fence) instruction (this instruction was introduced in the Pentium® III; see “The SFENCE Instruction” on page 784 for more information).

• A memory write to a different line of WC memory when all four WCBs already contain some updated bytes that have yet to be written to system memory.

• A cache line fill request when all four buffers are already in use and one or more of them contain WCB data.