The Previous Chapter
This chapter provided a detailed description of the software enhancement included in the 486 processor. This discussion is directly applicable to all subsequent IA32 processors and covered:
The on-die FPU.
The Alignment Checking Feature.
Paging-Related Changes.
Caching-Related Changes to the Programming Environment.
The Test Registers.
Instruction Set Changes.
New/Altered Exceptions.
This Chapter
This chapter provides an overview of the Pentium® processor's hardware design characteristics. This includes:
The Pentium® roadmap.
An overview of the Pentium® internal architecture.
An overview of the Pentium® FSB.
The Caches.
The Local APIC.
The Test Access Port (TAP). This discussion is directly applicable to all subsequent IA32 processors.
FRC Mode. This discussion is directly applicable to all subsequent IA32 processors up to and including the Pentium® III processor.
Soft Reset (INIT#). This discussion is directly applicable to all subsequent IA32 processors.
The Next Chapter
This chapter provides a description of the software enhancements incorporated in the Pentium® processor. This discussion is directly applicable to all subsequent IA32 processors. It includes:
The VM86 Extensions.
Protected Mode Virtual Interrupts.
The Debug Extension.
The Time Stamp Counter.
4MB Pages.
the Machine Check Architecture (MCA).
Performance Monitoring.
The Local APIC Register Set.
The MSRs Added.
Instruction Set Changes.
New/Altered Exceptions.
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