Snooping
General
The system processor(s) cache information from system memory and may modify the data in the cache but not perform a memory write on the FSB to update the original line in memory. The line in memory is then stale. For this reason, whenever any device (a processor or a device adapter) attempts to access system memory, the memory access must be made visible to the processors so they may snoop the memory address in their caches. In the Snoop Phase of the transaction, the processors provide the request initiator with the snoop result. If the snoop results in a hit on a modified line, the processor with the modified copy of the line asserts the HITM# signal in the Snoop Phase and then provides its modified copy of the line in the transaction's Data Phase.
A Memory Access Initiated by a Processor
When a processor has a miss on its internal caches and initiates a memory access on the FSB, the other processors latch the transaction, determine that it's a memory access, and submit the memory address to their internal caches for a lookup. In the transaction's Snoop Phase, they provide the Request Agent (i.e., the processor that experienced the miss) with one of the snoop results shown in Table 34-1 on page 827 (the values shown for the signals are electrical values). Please note that this section is not intended to be a detailed description including all aspects of snooping (for a detailed description, refer to “Pentium® 4 FSB Snoop Phase” on page 1225).
| Access Type | HIT# | HITM# | Description |
|---|---|---|---|
| Memory Read | 1 | 1 | A snoop miss on all processor caches. The Request Agent is permitted to read the line from system memory. |
| 0 | 1 | A snoop hit on one or more copies of the line that is still the same as the line originally read from system memory. Once again, the Request Agent is permitted to read the line from system memory. | |
| 1 | 0 | A snoop hit on a copy of the line in the modified (M) state. When the system memory controller detects this snoop result, it cancels its read of the line from system memory. In the transaction's Data Phase, the processor that asserted HITM# supplies the line to both the Request Agent (i.e., the other processor) and to the system memory controller. The system memory controller latches the line and uses it to update the stale copy of the line in memory. The processor that supplied the modified copy of the line changes the state of the line in its cache to indicate that it now the same as the one in memory. | |
| 0 | 0 | One or more of the Snoop Agents (i.e., the processors) need a little more time before supplying the actual snoop result. As a result, the Request Agent inserts wait states in the transaction's Snoop Phase until the actual snoop result is provided. | |
| Memory Write | 1 | 1 | A snoop miss on all processor caches:
|
| 0 | 1 | This is an illegal snoop result. If a processor has a copy of the line that is still the same as the one in memory, it must delete its copy and indicate a snoop miss (see the previous row). | |
| 1 | 0 | This won't happen. The area of memory is WB memory (as indicated by a processor having a modified copy of a line). If another processor has a write miss, it will initiate a Memory Read and Invalidate transaction, not a Memory Write. | |
| 0 | 0 | One or more of the Snoop Agents (i.e., the processors) need a little more time before supplying the actual snoop result. As a result, the Request Agent inserts wait states in the transaction's Snoop Phase until the actual snoop result is provided. |
A Memory Access Initiated by a Device Adapter
When a device adapter attempts to access system memory, the Root Complex must stall the access until it has sent a snoop transaction to the FSB and has obtained the snoop result. Otherwise, one of the following problems could arise:
The device adapter could read stale data from memory.
The device adapter could write some data into a stale line memory.
The processors may have a copy of the line that is still the same as the line in memory and would not be aware that a device adapter had changed one or more bytes within the line in memory. The cached copy of the line would be stale and the processor wouldn't know it. If the program that is currently executing on the processor core requested the stale data, bad things will result.
This discussion assumes that the system memory controller is embedded within the Root Complex (rather than residing on the FSB). The type of transaction that the Root Complex performs on the FSB as a snoop transaction depends on whether the device adapter is attempting a read or a write:
For a memory read access, the Root Complex performs a 0-byte Memory Read transaction.
For a memory write access, the Root Complex performs a 0-byte Memory Read and Invalidate transaction.
Table 34-2 on page 830 explains the possible snoop results of the transaction types.
| Snoop Type | Snoop Result | Description | |
|---|---|---|---|
| HIT# | HITM# | ||
| 0-byte Memory Read | 1 | 1 | A snoop miss. The device adapter is permitted to read the data from system memory. |
| 0 | 1 | A snoop hit on a copy of the line that is still the same as the line originally read from system memory. The device adapter is permitted to read the data from system memory. | |
| 1 | 0 | A snoop hit on a Modified (M) line. Although this started out as a 0-byte Memory Read transaction, it is transformed into a full line read. The processor supplies the modified line to the Root Complex and the Root Complex supplies the line to the memory controller and the requested read data to the device adapter. The stale line in memory is freshened. The processor changes the state of its line to show that it's now the same as the line in memory. | |
| 0 | 0 | One or more of the Snoop Agents (i.e., the processors) need a little more time before supplying the actual snoop result. As a result, the Request Agent inserts wait states in the transaction's Snoop Phase until the actual snoop result is provided. | |
| 0-byte Memory Read and Invalidate | 1 | 1 | A snoop miss. The device adapter is permitted to read the data from system memory. |
| 0 | 1 | This won't happen. Any processor that has a copy of the line in the E or S state deletes it and indicates a snoop miss. | |
| 1 | 0 | A snoop hit on a Modified (M) line. Although this started out as a 0-byte Memory Read and Invalidate (MRI) transaction, it is transformed into a full line MRI. The processor supplies the modified line to the Root Complex and the Root Complex supplies the line to the memory controller. The write data supplied by the device adapter is merged into the appropriate locations within the line and the line is written into system memory. The processor deletes its copy of the line (because it will not receive any of the device adapter's write data). | |
| 0 | 0 | One or more of the Snoop Agents (i.e., the processors) need a little more time before supplying the actual snoop result. As a result, the Request Agent inserts wait states in the transaction's Snoop Phase until the actual snoop result is provided. | |