Example Write To a PCI Express Device
The Write Receives the Defer Response
The previous section, “Example Read From a PCI Express Device” on page 1281, described the actions of the Root Complex upon receipt of a read transaction that targeted a device residing on the PCI bus in Figure 52-2 on page 1279. This section describes the same scenario, but replaces the read with a write transaction.
Refer to Figure 52-5 on page 1290 during this example. Assume that a processor initiates an IO or a memory-mapped IO write transaction that targets the IEEE 1394 FireWire controller on the PCI bus:
The write request is issued by the processor in BCLK cycle 1. The Root Complex latches the address and transaction type in Packet A and the Deferred ID (consisting of the processor's agent type, agent ID and the transaction ID) in Packet B. In addition, the DEN# (Defer Enable) signal is deasserted in Packet B giving the Root Complex permission to defer the transaction if required.
In the transaction's Snoop Phase, there is a snoop miss and the Root Complex asserts DEFER#, indicating that it will deliver either the Retry or Deferred response in the Response Phase.
The Root Complex asserts TRDY# at the start of BCLK cycle 4, indicating that it is ready to accept the write data. A single BCLK assertion of TRDY# is permitted because the Root Complex sampled DBSY# deasserted at the start of BCLK cycle 4.
The processor sampled TRDY# asserted and DBSY# deasserted at the start of BCLK cycle 5, granting it permission to take ownership of the Data Bus one BCLK cycle later to deliver the write data to the Root Complex.
The Root Complex starts driving the Deferred response to the processor at the start of BCLK cycle 5.
The processor samples DEFER# asserted at the start of BCLK cycle 5, giving it advance notice that the Root Complex intends to issue either the Retry or Deferred response.
The processor samples the Deferred response at the start of BCLK cycle 6, ending the Response Phase.
The processor drives out the write data and the data strobes at the start of BCLK cycle 6.
The processor also asserts DRDY#, indicating that it is driving valid data during BCLK cycle 6.
The processor does not, however, assert DBSY# because it's not necessary if the Request Agent can immediately supply a single clock's worth of write data.
The Root Complex uses the data strobes to latch the write data into an internal buffer during BCLK cycle 6.
The Root Complex samples DRDY# asserted at the start of BCLK cycle 7, validating the data it received during the previous BCLK cycle.
This completes the write transaction. However, because it received a Deferred response, the processor transfers the write request into its Deferred Transaction Queue to await the subsequent Deferred Reply transaction.
The Root Complex Delivers the Write Data to the Target
Refer to Figure 52-2 on page 1279. The Root Complex formulates a write packet and forwards it into the PCI Express fabric:
The packet is forwarded to the switch which, in turn forwards it to the PCI Express-to-PCI bridge.
The PCI bridge arbitrates for ownership of the PCI bus and initiates a PCI write transaction. The FireWire controller accepts the write data from the bridge.
The bridge forwards the reply packet to the switch which, in turn, forwards it to the Root Complex.
There are several possibilities:
- The transaction completed successfully. The good completion is stored in a buffer in the Root Complex. In this case, the Root Complex must indicate the no data response in the Response Phase of the Deferred Reply transaction (described in the next section).
- The transaction resulted in a PCI Target Abort from the target, indicating that it is broken. In this case, the Root Complex must indicate the hard failure response in the Response Phase of the Deferred Reply transaction.
- The transaction ended in a PCI Master Abort because no target responded to the transaction (i.e., DEVSEL# was not sampled asserted within four PCI clocks after the transaction's Address Phase completed). In this case, the Root Complex must indicate the hard failure response in the Response Phase of the Deferred Reply transaction.
- A PCI write parity error was detected. In this case, the Root Complex must indicate the hard failure response in the Response Phase of the Deferred Reply transaction.
The Root Complex Issues a Deferred Reply Transaction
General
Refer to Figure 52-6 on page 1293 during the following discussion. When the PCI transaction has completed, the Root Complex uses BPRI# to arbitrate for ownership of the Request Phase signal group.
Having acquired ownership of the Request Phase signal group, the Root Complex then issues a Deferred Reply transaction. During the Request Phase, the Root Complex acts as the Request Agent and the processor addressed by the Deferred ID (see Table 52-1 on page 1286) acts as the target of the transaction. The information indicated in Table 52-1 is driven out during the transmission of packets A and B. All agents on the FSB latch the two packets during the Request Phase.
The Original Request Agent Is Selected
All of the agents with outstanding deferred transactions compare the DID field latched in packet A (from A[23:16]#) to determine if this is the reply to a previously-deferred transaction in their Deferred Transaction Queues. The Request Agent that originated the write has a match on its agent type, agent ID, and transaction ID.
The Root Complex Provides the Snoop Result
Until the Snoop Phase, the Root Complex acts as the Request Agent of the Deferred Reply transaction, but something interesting happens in the Snoop Phase. The Deferred Reply transaction is never snooped by the FSB Snoop Agents. Rather, the snoop result is supplied by the Root Complex (i.e., the agent that deferred the transaction earlier) with the snoop result obtained from caches on the PCI bus (there are none) when it performed the write. Since system designs do not permit PCI agents to cache memory information, the snoop result delivered on HIT# and HITM# indicates a cache miss (both are deasserted). In addition, the DEFER# signal is not asserted (DEN# is always deasserted in request Packet B during a Deferred Reply transaction).
Role Reversal in the Response Phase
Once the snoop result is delivered to the processor by the Root Complex, the Response Phase of the transaction is entered. The role reversal is now complete—the Root Complex initiated the Deferred Reply transaction, but now reverts to its original role in the original transaction as the Response Agent. The processor started out as the target and now reverts to its original role as the Request Agent. The processor and the Root Complex have reverted to the roles they originally played when the transaction was first initiated by the processor. Depending on how the transaction completed on the PCI Express side of the Root Complex, the Root Complex delivers one of the following responses:
If the transaction completed successfully and the data was written to the target without error, the Root Complex must indicate the no data response in the Response Phase of the Deferred Reply transaction.
If the transaction resulted in a Target Abort from the target, indicating that it is broken, the Root Complex must indicate the hard failure response in the Response Phase of the Deferred Reply transaction.
If the transaction ended in a Master Abort because no target responded to the transaction (i.e., DEVSEL# was not sampled asserted within four PCI clocks after the transaction's Address Phase completed), the Root Complex must indicate the hard failure response in the Response Phase of the Deferred Reply transaction.
If a PCI write parity error was detected, the Root Complex must indicate the hard failure response in the Response Phase of the Deferred Reply transaction.
There is No Data Phase
The write data was transferred to the Root Complex in the Data Phase of the original write transaction that was deferred. The Deferred Reply transaction therefore completes with the Response Phase.
All Trackers Retire the Transaction
The no data response indicates that the data was accepted without error by the PCI target. Once the processor that initiated the original transaction as well as the other FSB agents detect the no data response, they retire the transaction from their Deferred Transaction Queues.