Chapter 30. Pentium® III Hardware Overview

The Previous Chapter

This chapter described the first Xeon processor. It was based on the Pentium® II processor. This included:

• The Cartridge.

• FSB Protocol Alteration (GTL+ to AGTL+).

• FSB Arbitration.

• SMBus (System Management Bus). This is an introduction to the SMBus. A detailed description of the SMBus is outside the scope of this book.

• PSE-36 Mode. This discussion is directly applicable to all subsequent IA32 processors.

This Chapter

This chapter provides a description of the Pentium® III processor's hardware design characteristics. This includes:

• One product = three product lines.

• Pentium® II/Pentium® III differences.

• The Pentium® III/Xeon/Celeron roadmap.

• The L1 Caches.

• The L2 Cache.

• The Data Prefetcher.

• SSE introduced.

• The WCBs were enhanced.

• Additional Writeback Buffers.

• SpeedStep Technology.

The Next Chapter

This chapter provides a detailed description of the software enhancements introduced in the Pentium® III processor. This discussion is directly applicable to all subsequent IA32 processors. It includes:

• The Streaming SIMD Extensions (SSE).

• The SIMD FP exception.

• The Serial Number feature. This feature was discontinued with the advent of the Pentium® 4 processor.

• CPUID Enhanced.

• Brand Index feature.