The Interrupt Acknowledge Transaction
Background
An IA32-based system incorporates an interrupt controller that receives interrupt requests from IO devices and passes them on to the processor (or to the processor cluster). The interrupt controller will either consist of a pair of cascaded 8259A's in a single processor system (see “Before the Advent of the APIC” on page 1498), or an IO APIC module in a multiprocessor system.
Refer to Figure 54-1 on page 1304. In earlier chipsets, the interrupt controller was incorporated in the South Bridge. It is found in the ICH (the IO Control Hub) in the chipsets that are prevalent as of this writing. This is a strategically convenient place for it because the interrupt requests from PCI and legacy ISA targets (typically residing on the LPC—Low-Pin Count—bus) can easily be connected to it.
Assuming that the system uses the 8259A interrupt controllers, the interrupt controller asserts its INTR (Interrupt Request) output when it detects any interrupt requests from device adapters (see Figure 54-1 on page 1304). The INTR signal line is connected to the processor's INTR input pin (also referred to as the LINT0 pin). In response to its assertion, the processor takes the following actions:
Assuming that recognition of external interrupts is enabled (in other words, the programmer has not executed the CLI instruction), the processor will recognize the request when it completes the execution of the current instruction.
The processor suspends execution of the interrupted program.
The processor generates an Interrupt Acknowledge transaction on its FSB to read the interrupt vector (of the highest priority request) from the interrupt controller.
The North Bridge or MCH (Memory Control Hub) passes the request for the interrupt vector to the South Bridge or ICH. In a North Bridge/South Bridge configuration, the North Bridge generates a PCI (or PCI-X) Interrupt Acknowledge to request the vector from the interrupt controller embedded within the South Bridge.
The South Bridge or ICH passes the vector back to the North Bridge or MCH.
The North Bridge or MCH passes the vector to the processor.
The processor uses the 8-bit vector as an index into the Interrupt Table in memory and reads the new CS:EIP value from the selected entry.
The processor pushes the contents of its CS, EIP and EFlags registers into stack memory (to mark its place in the interrupted program).
The processor then disables recognition of additional external interrupts (i.e., it clears the EFlags[IF] bit).
Using the new CS:EIP value, the processor jumps to the target interrupt service routine and executes it.
The Transaction Details
Earlier, pre-Pentium® Pro IA32 processors generated two, back-to-back Interrupt Acknowledge transactions when an interrupt was delivered on the INTR pin:
One to command the interrupt controller to prioritize its pending requests.
The second to request the interrupt vector for the most important one.
Starting with the P6 processor family, however, the processor only generates one Interrupt Acknowledge transaction. This transaction has the following characteristics:
In Packet A, the request type issued on REQ[4:0]# is 01000b (this is the logical, not electrical, value). For more information, refer to Table 49-5 on page 1216.
Although the content of the address bus in packet A is “don't care,” it must be stable and is factored into the address parity on AP[1:0]#.
In Packet B, REQ[4:0]# is 00x00b, where x is “don't care.”
In Packet B, with the exception of A[15:8]# (the Byte Enables) and A[4]# (DEN#, Defer Enable), the content of the address bus is “don't care.”
In Packet B, DEN# is asserted, granting the Response Agent permission to Defer or Retry the transaction if it so chooses.
In Packet B, only BE[0]# is asserted, indicating that it's a single-byte read to obtain the interrupt vector over data path 0 (D[7:0]#).
The Root Complex is the Response Agent
In Figure 54-2 on page 1305, the Root Complex acts as the Response Agent if the interrupt controller resides within or beneath the Root Complex. Since it may take some time to obtain the vector, the Root Complex may choose to issue the Deferred response to the processor. The Root Complex forwards the vector request to the device containing the interrupt controller for fulfillment. When the Root Complex receives a reply packet containing the 8-bit vector, it initiates a Deferred Reply transaction on the FSB to deliver the vector to the processor.
