Alignment Checking Feature

The performance problem associated with misaligned transfers was introduced in “Misaligned Transfers Affect Performance” on page 43. The 486 processor introduced the Alignment Check feature. There are three elements associated with this feature:

• CR0[AM] (see Figure 19-2 on page 434). While the programmer is engaged in fine tuning the performance of a program, the OS or a debug program sets CR0[AM] = 1.

• EFlags[AC] (see Figure 19-10 on page 449). Assuming that CR0[AM] = 1 and that the currently executing task has EFlags[AC] = 1 (because the AC bit was set to one in the EFlags register image in the task's TSS), any misaligned data or stack access attempt causes an Alignment Check exception (exception 17).

  Figure 19-10. Bits Added to EFlags in the 486

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• Exception 17. The Alignment Check exception (exception 17) was added to the IA32 architecture with the advent of the 486 processor. See “Exception 17 (Alignment Check) Added” on page 460.