Address Mapping

The Linear vs. the Physical Memory Address

As discussed in earlier chapters, when addressing memory the post-286 processor forms the 32-bit memory address by adding the 32-bit offset to the segment start address. The resultant 32-bit address is referred to as the linear address. If the OS has not enabled the processor's paging capability (CR0[PG] = 0), the linear address is the address that is used to address memory. In other words, the linear address and physical address are the same.

On the other hand, if the processor's paging capability is enabled (CR0[PG] = 1), the Paging Unit can convert, or map, the linear address to any physical memory address in the 4GB memory space. This is accomplished by using the 32-bit linear address to perform a lookup the Page Directory and Page Tables.

The GDT Purpose and Location

The GDTR (GDT register) contains the base linear address (and size) of the GDT in memory. The GDT entries define segments that are common to all applications as well as special segments (e.g., a TSS) used by the OS kernel.

It's important to note that the contents of the GDTR does not change when a task switch occurs. This means that all tasks use the same GDT to access the pool of common segments.

CR3 contains the base physical memory address of the Page Directory and is sometimes referred to as the PDBR (Page Directory Base address Register). When a task switch occurs, CR3 is changed to point to the Page Directory for the current task (by updating it from the CR3 field in the new task's TSS). It is important that the Page Directory for every task be set up to map accesses to the GDT to the same range of locations in physical memory. The goal of a shared GDT would be defeated if each task mapped the GDT's linear address range to different physical memory ranges. They would be using different GDTs. For more information on Paging, refer to the section entitled “Paging-Related Issues” on page 207 and the chapter entitled “386 Demand Mode Paging” on page 209.

The LDT Purpose and Location

Whenever a task switch occurs, the processor updates the LDTR from the new task's LDT selector field. The memory segments that can be used by the new task consists of those defined by the GDT (which remains the same for all tasks) and those defined by the task's LDT as local to this task.

The OS sets up the LDT selector field of each task's TSS to point to that task's LDT descriptor in the GDT. Ideally, the OS sets up the TSS fields so that each task has its own, distinct LDT that defines the segments local to the task. However, the OS could set them up so all tasks shared one LDT, or so some tasks but not others shared an LDT.

Paging-Related Issues

Background

When Paging is enabled, the processor's Paging Unit intercepts all linear memory addresses and converts them to physical memory addresses. The Paging Unit deals with two, distinct memory ranges: 4GB of linear memory space and 4GB of physical memory address space. It considers each space as being subdivided into 4KB pages of information.

When presented with a 32-bit linear memory address by the segmentation logic, the address naturally lies within some 4KB range of linear memory space (i.e., a linear memory page). The upper 20 bits of the linear address identify which of the one meg (1,048,576d) linear memory pages is being addressed. The Paging Unit then uses a directory lookup mechanism to find out which of the one meg physical memory pages the linear page (identified by the upper 20 bits of the linear address) should be mapped to. The Paging Unit uses the upper 20 bits of the linear address to perform a lookup in the Page Directory and in the selected Page Table. The upper 20-bits of the physical page address is produced by this lookup and replaces the linear page address (i.e., the upper 20 bits of the linear address). The lower 12 bit portion of the linear address remains untouched—it identifies exactly which of the 4096d locations within the page is being addressed. In this manner, the Paging Unit converts the 32-bit linear address into a corresponding 32-bit physical memory address.

The tables that the Paging Unit consults to make the address conversion are in memory and CR3 contains the start physical memory address of the top-level directory used for the lookup and address conversion.

Each Task Can Have Different Linear-to-Physical Mapping

Each time that a task switch occurs, the processor updates CR3 with the physical start memory address of the new task's Page Directory. CR3 is also referred to as the Page Directory Base Register, or PDBR. In other words, by placing different addresses in the CR3 field of each TSS, each task can use a different set of tables to perform the linear-to-physical address conversion.

TSS Mapping Must Remain the Same for All Tasks

The linear-to-physical mapping for the range of addresses associated with all TSS segments must remain constant for all tasks. In other words, these linear address ranges must be translated identically by all tasks. When a task switch occurs from task A to task B:

• The register set's current contents is saved in task A's TSS (using task A's Page Directory to perform the translation of the TSS's linear range to its physical range).

• The task switch then occurs and the register set is reloaded from task B's TSS segment.

• The Link field of task B's TSS is set to the GDT selector for task A's TSS descriptor.

• CR3 is loaded with the base address of task B's Page Directory.

• When task B has completed and it's time to resume task A, the processor must restore its register set from task A's TSS. It uses task B's Page Directory to perform the translation of task A's TSS linear range to its physical range.

If task B's Page Directory translates task A's TSS linear range to a different physical range than task A's page directory translated it when storing the register image, the processor would restore the wrong information to the processor's register set.

Placement of a TSS Within a Page(s)

An unrecoverable error results if a GP exception or a Page Fault (due to the target physical page not being in memory) occurs after the processor has started to read the TSS for the new task when performing a task switch. To prevent this, the following rules must be adhered to:

• If possible, place the entire first 104d bytes of the TSS (i.e., the part accessed during a task switch) within a single page. If necessary, the TSS can straddle a page boundary (i.e., an address divisible by 4KB), but both pages must be present in memory (P = 1 in both of their Page Table Entries).

• The page or pages that contain the old and new TSSs must be present in memory and must be marked read/write (in the Page Table Entry).